Technical information

SH7285 Group
Example of Initialization
REJ06B0860-0100/Rev.1.00 June 2009 Page 7 of 21
2.3 CPG Setting
The figure below shows the flow chart of setting CPG. Internal peripheral modules are in module standby mode after the
reset is canceled. The sample program clears the module standby function for internal peripheral module after setting the
Frequency control register (FRQCR), MTU2S clock frequency control register (MCLKCR), and AD clock frequency
control register (ACLKCR). For details on these registers, refer to the SH7285 Group Hardware Manual.
Start
End
Set the AD clock frequency control register
(ACLKCR)
• Set the Frequency control register (FRQCR)
(1) STC bit:
Set the bus clock division ratio (1 to 8)
(2) IFC bit:
Set the internal clock division ratio (1 to 8)
(3) PFC bit:
Set the internal clock division ratio (1 to 8)
Clear the module standby function
(STBCR3 to STBCR6)
• Clear the module standby function (STBCR3 to STBCR6)
Clear the module standby function for internal peripheral modules.
Set the Frequency control register (FRQCR)
(1)
Set the MTU2S clock frequency control register
(MCLKCR)
• Set the MTU2S clock frequency control register (MCLKCR)
- MSDIVS bit:
Set the MTU2S clock division ratio (1 to 4)
• Set the AD clock frequency control register (ACLKCR)
- ASDIVS bit:
Set the AD clock division ratio (1 to 4)
Note: Execute 32 NOP instructions just after setting the FRQCR.
Refer to 4.4.1 Frequency Control Register (FRQCR) in the SH7280 Group Hardware Manual.
Figure 3 Flow Chart of CPG Setting