Technical information

SH7285 Group
Example of Initialization
REJ06B0860-0100/Rev.1.00 June 2009 Page 6 of 21
FRQCR MCLKCR ACLKCR
Bus interface
CK
CPG control unit
Clock frequency
control circuit
Standby control circuit
EXTAL
XTAL
PLL circuit
(×8)
Divider
MTU2S clock
(Mφ, Max. 100 MHz)
AD clock
(Aφ, Max. 50 MHz)
Internal clock
(Iφ, Max. 100 MHz)
Peripheral clock
(Pφ, Max. 50 MHz)
Bus clock
(Bφ = CK, Max. 50 MHz)
OSCCR
Crystal
oscillator
On-chip oscillator
HPB bus
STBCR STBCR6STBCR2 STBCR3 STBCR4 STBCR5
×1
×1/2
×1/4
×1/8
[Legend]
Frequency control register
MTU2S clock frequency control register
AD clock frequency control register
Standby control register
Standby control register 2
FRQCR:
MCLKCR:
ACLKCR:
STBCR:
STBCR2:
Standby control register 3
Standby control register 4
Standby control register 5
Standby control register 6
Oscillation stop detection control register
STBCR3:
STBCR4:
STBCR5:
STBCR6:
OSCCR:
Oscillation
stop detection
circuit
Oscillation stop
detection
Figure 2 CPG Block Diagram