Technical information

SH7285 Group
Example of Initialization
REJ06B0860-0100/Rev.1.00 June 2009 Page 5 of 21
2.2 CPG Operation
CPG generates the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (Mφ), and AD clock (Aφ). It
also controls the clock in low power mode.
The following table gives an overview of the CPG.
Figure 2 shows the CPG block diagram.
Table 1 CPG Overview
Item Description
Generate clock
• Internal clock (Iφ):
• Bus clock (Bφ):
• Peripheral clock (Pφ):
• MTU2S clock (Mφ):
• AD clock (Aφ):
Used by the CPU
Used by the external bus interface
Used by the internal peripheral module
Used by the MTU2S module
Used by the AD module
Change frequency
• Sets frequencies for internal clock, bus clock, peripheral clock, MTU2S
clock, and AD clock independently using the PLL (Phase Locked
Loop) circuit and divider circuit in the CPG.
• Changes frequency by software using the Frequency control registers
(FRQCR, MCLKCR, and ACLKCR).
Control the low power mode
Stops clock in sleep mode or software standby mode. Stops the module
specified by module standby function.