Technical information
SH7285 Group
Example of Initialization
REJ06B0860-0100/Rev.1.00 June 2009 Page 16 of 21
3.7 Sample Program Listing "cpg.c" (2/2)
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/*""FUNC COMMENT""**************************************************************
* ID :
* Outline : CPG setting
*------------------------------------------------------------------------------
* Include : <machine.h> and "iodefine.h"
*------------------------------------------------------------------------------
* Declaration : void io_set_cpg(void);
*------------------------------------------------------------------------------
* Description : Initializes the clock pulse generator (CPG) as follows:
* : I-clock = 100MHz, B-clock = 50MHz, P-clock = 50MHz,
* : M-clock = 50MHz, and A-clock = 50MHz.
* : And then supplies clock to all peripheral modules.
*------------------------------------------------------------------------------
* Argument : void
*------------------------------------------------------------------------------
* Return Value : void
*------------------------------------------------------------------------------
* Note : This function is an example of CPG setting at the input clock
* : of 12.5MHz.
*""FUNC COMMENT END""**********************************************************/
void io_set_cpg(void)
{
/* ==== CPG setting ==== */
CPG.FRQCR.WORD = 0x0101; /* Clock-in = 12.5MHz */
/* I-clock = 100MHz */
/* B-clock = 50MHz */
/* P-clock = 50MHz */
nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop();
nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop();
nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop();
nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop();
CPG.MCLKCR.BYTE = 0x41; /* M-clock = 50MHz */
CPG.ACLKCR.BYTE = 0x41; /* A-clock = 50MHz */
/* ==== Module Stanby Clear ==== */
STB.CR3.BYTE = 0x02; /* HIZ, MTU2S, MTU2, POE2, */
/* IIC3, ADC0, Reserve(1), Reserve(0) */
STB.CR4.BYTE = 0xe2; /* Reserve(1), Reserve(1), Reserve(1), SCIF3, */
/* Reserve(0), CMT, Reserve(1), Reserve(0) */
STB.CR5.BYTE = 0x12; /* SCI0, SCI1, SCI2, Reserve(1), */
/* SCI4, ADC1, Reserve(1), SSU */
STB.CR6.BYTE = 0x9f; /* USB: Using USBXTAL/USBEXTAL for USBCLK. */
}
/* End of File */