Technical information

Functional Overview
2.3.2 Flash Memory
Rev.1.01 2008.05.07 2-16
REJ11J0012-0101
2
Table 2.3.2 Bus State Controller Setting (Flash Memory Write/Read)
User Area Target Device Bus State Controller Setting
CS0 S29GL064A90TFIR4 CS0 space bus control register :CS0BCR
Initial value: H'36DB 0600 (at MD_BW ="L")
Recommended setting value : H'1000 0400
• Idle cycles between write-read cycles and write-write cycles
IWW[2:0] = B'001; 1 idle cycle inserted
• Data bus specification
BSZ[1:0] = B'10 ; 16-bit bus width
CS0 space wait control register: CS0WCR
Initial value: H'0000 0500
Recommended setting value : H'0000 0AC1
• Assert delay cycle from RD# and WEn# to address and CS0#
assert
SW[1:0] = B'01; 1.5 cycles
• Number of access wait cycle
WR[3:0] = B'0110; 5 cycles
• CS0# negate delay cycle from RD# and WEn# negate to
address
HW[1:0] = B'01; 1.5 cycles
<Write/Read Timing>
Write1 Write2 Read1
DATA DATA DATA
tDF(OE)
tDF(CE)
ta(CE1)
ta(AD)
ta(OE)
tWDH1
tWDD1
tWDH1
tWDD1
tWED1tWED1tWED1tWED1
tRSDtRSD
tCSD1
tCSD1
tCSD1
tCSD1
tCSD1tCSD1
tAD1tAD1
tAD1
tAD1
tAD1tAD1
tRDH1
tRDS1tDH
tDS
tDH
tDS
tOEH
tAH
tAS tCH
tWPtWPH tWP
tAHtAS
tWPH
tCHtWP
tCS
tWP
tRCtRC
tWCtWC
T1T2Tw4T1 Tw1 Tw2 Tw1 Tw2 T2 T1 Tw1 Tw2 Tw3 T2Tf Tf Taw1Taw1Th Th Th TfTw4Tw3 Tw3 Tw4 Tw5Tw5 Tw5
CKIO
A21-A1
CS0#
RD#
WE0#
D15-D0
Figure 2.3.2 Example of Flash Memory Read/Write Access Timing