REJ10J1351-0101 SH7619 CPU Board M3A-HS19 32 User's Manual Renesas 32-Bit RISC Microcomputers SuperH RISC engine Family/SH7619 Group TM Rev. 1.
Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
Table of Contents Chapter1 Overview .............................................................................................................................. 1-1 1.1 Overview .................................................................................................................................................................... 1-2 1.2 Configuration .................................................................................................................................................
3.2.2 Features of Switches and LEDs ...................................................................................................................... 3-18 3.3 Dimensions............................................................................................................................................................... 3-20 Appendix..............................................................................................................................................
Chapter1 1-1 Overview Chapter1 Overview
Overview 1 1.1 Overview 1.1 Overview The M3A-HS19 is a CPU board designed to evaluate the feature and performance of the SH7619 Group of Renesas Technology original MCU, as well as developing and evaluating the application software for the MCUs.
Overview 1 1.3 External Specification 1.3 External Specifications Table 1.3.1 lists external specifications. Table 1.3.1 External Specifications No. 1 2 Items Description CPU SH7619 Memories • Input (XIN) clock: 15.625 MHz • Bus clock: 62.
Overview 1 1.4 1.4 Appearance Figure 1.4.1 shows the appearance of the M3A-HS19. Figure 1.4.1 M3A-HS19 Appearance Rev.1.
Overview 1 1.5 M3A-HS19 Block Diagram 1.5 M3A-HS19 Block Diagrams Figure 1.5.1 shows the system block diagram. Serial port connector (RS-232C x 2, RS-422 x 1) H-UDI (14-pin) 16-bit H-UDI LAN connector SCIF /SCI HIF Expansion connector (HIF bus) GPIO/ EtherC SH7619 Other Peripheral Functions Expansion connector (CPU bus) BSC 16-bit 16-bit 16-bit Bus switch PCMCIA connector SDRAM SDRAM (16MB) (16MB) Flash Memory (4MB) (4MB) SH7619 CPU Board M3A-HS19 Figure 1.5.
Overview 1 1.6 M3A-HS19 Board Overview 1.6 M3A-HS19 Board Overview Figure 1.6.1 shows the M3A-HS19 board overview. Top view of the component side SW1 Power switch LED5 Power LED U5 PCMCIA power control IC U7,U8,U9 Bus switch LED1-4 User LED J7 Power connector J6 H-UDI connector (14-pin) JP9 Power switching jumper U6 RS-232C driver J14 AC adaptor jack J2 RS-232C serial connector U12, U16 3.3V/1.8V regulator IC X3 25MHz oscillator U1 SH7619 X1 15.
Overview 1 1.6 M3A-HS19 Board Overview Table 1.6.1 lists major components mounted on the M3A-HS19 Table 1.6.
Overview 1 1.7 M3A-HS19 Memory Mapping 1.7 M3A-HS19 Memory Mapping Area 0 bus width: (Default) MD3 = 0 •••16-bit Data alignment: MD5 = 0(ON) •••Big endian MD5 = 1(OFF) •••Little endian (SW4-1) Figure 1.7.1 show the memory mapping examples of the SH7619 on the M3A-HS19. Logical Address [31~29] Area Cacheable/Non-cacheable 000~011 P0 Cacheable 100~ P1 Cacheable 101~ P2 Non cacheable 110~ P3 Cacheable 111~ P4 Non-cacheable (on-chip I/O) etc.
Overview 1 1.8 Absolute Maximum Ratings 1.8 Absolute Maximum Ratings Table 1.8.1 lists the absolute maximum ratings. Table 1.8.1 Absolute Maximum Ratings Symbol Parameter Value Remarks VCC 5 V system power supply voltage -0.3 to 6.0 V Relative to VSS 3VCC 3.3 V system power supply voltage -0.3 to 3.8 V Relative to VSS 1.8VCC 1.8 V system power supply voltage -0.3 to 2.1 V Relative to VSS Topr Operating temperature -5 to 55°C No condensation, no corrosion gas allowed.
Overview 1 1.8 Absolute Maximum Ratings This page intentionally left blank Rev.1.
Chapter2Features and Specifications Chapter2 Features and Specifications 2-1
Features and Specifications 2 2.1 Features 2.1 Features Table 2.1.1 lists the functional modules. Table 2.1.1 Functional Modules Section 2.2 2.3 Features Description CPU SH7619, clock mode 1 Memories • Input (XIN) clock: 15.625 MHz • Bus clock: 62.5 MHz, max. • CPU clock: 125 MHz, max. • U Memory (CPU) • 16-KB memory • Flash Memory • S29GL032A90TFIR4: 1 (4 MB) • SDRAM • EDS1216AATA-75E: 1 (16 MB) • EEPROM • S-93C76AFT-V-G: 1 (8 KB, 512 x 16) 2.
Features and Specifications 2 2.2 CPU 2.2 CPU 2.2.1 SH7619 The M3A-HS19 CPU board includes the SH7619, the 32-bit RISC MCU operates with a maximum frequency of 125 MHz. The SH7619 is equipped with an Ethernet controller that includes an IEEE802.3u compliant Media Access Controller and a Physical Layer Transceiver. Moreover, the SH7619 has both a 16-KB U memory (RAM) and a 16-KB instruction/data unified cache memory.
Features and Specifications 2 2.3 Memory 2.3 Memory The M3A-HS19 includes the SH7619 on-chip U memory, an external flash memory, external SDRAM and EEPROM. Details are described below (Except the PC card). 2.3.1 SH7619 U Memory and Cache Memory The SH7619 has a 16-KB (RAM) U memory module (address: H’E55FC000~H’E55FFFFF) and a 16-KB instruction/data-unified cache memory. 2.3.2 Flash Memory S29GL032A90TFIR4 (Standard component) The M3A-HS19 comes standard with a flash memory listed in Table 2.3.
Features and Specifications 2 2.3.2 Flash Memory S29GL032A90TFIR4 (Standard component) Table 2.3.
Features and Specifications 2 2.3.3 External Synchronous DRAM 2.3.3 External Synchronous DRAM (SDRAM) The M3A-HS19 is provided with a 16-MB synchronous DRAM (SDRAM) as an external main memory. The SDRAM is controlled by the SH7619 on-chip bus state controller. The SDRAM is accessed in 16-bit bus. Table 2.3.3 lists SDRAM specifications used on the M3A-HS19, and Figure 2.3.3 shows its block diagram. Table 2.3.
Features and Specifications 2 2.3.3 External Synchronous DRAM A power-on sequence is required to use a SDRAM. Power-on sequence is to initialize the pin function controller (PFC), set registers in the bus state controller and write data in the SDRAM mode register. Table 2.3.4 lists the access address when writing in the SDRAM mode register on the CS3 space. Table 2.3.
Features and Specifications 2 2.3.3 External Synchronous DRAM Figure 2.3.4 shows a timing example of SDRAM mode register writing.
Features and Specifications 2 2.3.3 External Synchronous DRAM Table2.3.5 lists setting examples of the bus state controller with SH7619 bus clock at 62.5 MHz. Figure 2.3.5 shows the SDRAM single read/write timing example. Table2.3.5 Setting Example of Bus State Controller (SDRAM Read/Write) User Area CS3 Applicable Device EDS1216AATA-75E Rev.1.01 Oct 28, .
Features and Specifications 2 2.3.
Features and Specifications 2 2.3.4 External EEPROM 2.3.4 External EEPROM The M3A-HS19 is provided with an EEPROM for storing MAC address. Access to the EEPROM is enabled by using the SH7261 I/O ports (PC03, PC02, PC01 and PC00). A MAC address consists of 48-bit numbers. Table 2.3.6 lists instruction sets, and Figure 2.3.6 shows the block diagram of CPU and EEPROM connection. Figure 2.3.7 shows the EEPROM-AC timing and Figure 2.3.8 shows EEPROM-read/write timing.
Features and Specifications 2 2.3.4 External EEPROM AC characteristics Clock pulse width SK 1 μsec or more 0 sec or more 1 μsec or more Writing Enabled Data CS Deselect CS setup 400 nsec or more 200 nsec or more DI Setup 200 nsec or more Hold 200 nsec or more Hi-Z Hi-Z DO Within Within 800 nsec 800 nsec Output delay time Output disabled time Within 500 nsec Output Enabled Data Figure 2.3.
Features and Specifications 2 2.4 Serial Port Interface 2.4 Serial Port Interface The SH7619 MCU mounted on the M3A-HS19 is provided with a 3 channel’s of the Serial Communication Interface with FIFO (SCIF). SCIF channel 0 is connected to the 2-pin serial port connector, SCIF channel 2 is connected to the D-sub 9-pin serial port connector, and SCIF channel 1 is connected to the 4-pin serial port connector. Figure 2.4.1 shows the block diagram of the serial port interface. Figure 2.4.
Features and Specifications 2 2.5 PCMCIA Card Interface 2.5 PCMCIA Card Interface The SH7619 MCU mounted on the M3A-HS19 is compliant with the JEIDA 4.2 (PCMCIA2.1 Rev.2.1). However, only 3.3 V interface PC card is supported. An on-chip bus state controller (BSC) and a PFC control the PC card. High byte and low byte of the data is switched at the bus switch on the M3A-HS19. When the byte order of the SH7619 is big-endian, the order of the PC card connector is little-endian (IOIS16#: ”L”).
Features and Specifications 2 2.6 LAN Port Interface 2.6 LAN Port Interface An IEEE 802.3 compliant (MAC layer) Ethernet controller and an IEEE802.3/802.3u compliant (10/100 Mbps Ethernet PHY) physical layer transceiver are embedded in the SH7619 MCU. Figure 2.6.1 shows the block diagram of LAN port interface. 3.3 V SH7619 (U1) LED1 Yellow LED2 Yellow LED3 Yellow LED4 Yellow SPEED100# LINK# CRS# 3.
Features and Specifications 2 2.7 I/O Port 2.7 I/O Port Following I/O ports on the M3A-HS19 can be configured by the SH7619 MCU. These ports are multiplexed pins with up to four features. Some pins have several initial features for normal mode and HIF (Host Interface) boot mode. Features can be controlled by PFC (pin function controller).
Features and Specifications 2 2.7 I/O Port Table 2.7.
Features and Specifications 2 2.7 I/O Port Table 2.7.
Features and Specifications 2 2.8 Power Supply Circuit 2.8 Power Supply Circuit The main power supply input 5 V DC to the M3A-HS19 and it generates 3.3 V and 1.8 V using a regulator. It is an adjustable output voltage regulator to generate a desired voltage by changing resistance values. A through-hole is provided with the M3A-HS19 to input 1.8 V DC from an external power supply. The PC card power supply is controlled by software. Figure 2.8.1 shows the schematic diagram of the power supply circuit.
Features and Specifications 2 2.9 Clock Module 2.9 Clock Module The clock module on the M3A-HS19 consists of following three blocks; • • • A block connecting X1 (oscillator) output to SH7619 EXTAL A block connecting X2 (ceramic resonator) to EXTAL and XTAL (Optional) A block connecting X3 (oscillator) to CK-PHY An on-chip oscillator (15.625 MHz) is connected to the SH7619 MCU to provide an operating clock. Another on-chip oscillator (25.
Features and Specifications 2 2.10 Reset Module 2.10 Reset Module Reset module controls reset signals connected to the SH7619 MCU, a flash memory and connectors. Software controls to reset PCMCIA connector. Figure 2.10.1 shows the schematic diagram of resets. H-UDI connector RESET# Reset IC output delay time: td = 0.34×Cd(pF)µsec = 34 ms ) ) Reset IC output detect voltage: Vs = 1.25× Ra+Rb = 2.5 V Rb Expansion connector RESET# 3.3 V 3.
Features and Specifications 2 2.11 Interrupt Switch 2.11 Interrupt Switch Push-button switches are connected to the SH7619 NMI pin and IRQ0 pin. Interrupts are connected to IRQ7 from an expansion connector and a PCMCIA connector. Figure 2.11.1 shows the schematic diagram of interrupts. 3.3 V SH7619 (U1) NMI SW 5 LVC14(U14) NMI switch 3.
Features and Specifications 2 2.12 E10A-USB Interface 2.12 E10A-USB Interface The M3A-HS19 is provided with a 14-pin H-UDI connector to embed the E10A-USB emulator. Figure 2.12.1 shows the block diagram of the E10A-USB interface. 3.3 V 3.3 V H-UDI connector (J6) SH7619 (U1) UVCC TCK 8 10 12 NC 11 TCK 1 TRST# TRST# TDO GND NC GND TMS 13 GND 14 GND TDI (GND) 3 TDO 4 5 TMS 6 TDI 9 ASEMD# 7 RES# RES# Reset Figure 2.12.1 E10A-USB Interface Rev.1.01 Oct 28, .
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Chapter3Operational Specifications Chapter3 Operational Specifications 3-1
Operational Specifications 3 3.1 M3A-HS19 Connector 3.1 M3A-HS19 Connectors Figure 3.1.1 shows the connector assignments on the M3A-HS19. Top view of the component side J6 H-UDI connector J7 Power supply connector J1 RS-232C (ch1) serial connector (optional) J14 AC adapter jack J2 RS-232C (ch2) serial connector J15 GND pin for test J8 1.
Operational Specifications 3 3.1.1 UART Connector Pin (J1) 3.1.1 UART Connector Pin (J1) The M3A-HS19 is provided with an UART connector pin (J1). Figure 3.1.2 shows the pin assignment for the UART connector (J1). Top view of the component side 1 2 J1 UART Board Edge Figure 3.1.2 Pin assignment for UART Connector (J1) Table 3.1.1 lists the pin assignment for the UART connector (J1). Table 3.1.1 Pin assignment for UART Connector (J1) Pin no. 1 Signal Name RXD (PE16/HIFD07/RXD0/D23) Rev.1.01 Oct.
Operational Specifications 3 3.1.2 UART Connector (J2) 3.1.2 UART Connector (J2) The M3A-HS19 is provided with an UART connector (J2). Figure 3.1.3 shows the pin assignment for the UART connector (J2). 1 6 5 9 Top view of the component side Board edge J2 1 6 5 9 Board edge Side view Figure 3.1.3 Pin assignment for UART Connector (J2) Table 3.1.2 lists the pin assignment for the UART connector (J2). Table 3.1.2 Pin assignment for UART Connector (J2) Pin no. Signal Name Pin no.
Operational Specifications 3 3.1.3 RS-422 Connector Pin (J3) 3.1.3 RS-422 Connector Pin (J3) The M3A-HS19 is provided with an RS-422 connector pin (J3). Figure 3.1.4 shows the pin assignment for the RS-422 connector pin (J3). Top view of the solder side Top view of the component side J3 1 2 3 4 1 2 3 RS-422 4 Board edge Board edge Figure 3.1.4 Pin assignment for RS-422 Connector Pin (J3) Table 3.1.3 lists the pin assignment for the RS-422 connector pin (J3). Table 3.1.
Operational Specifications 3 3.1.4 PCMCIA Connector (J4) 3.1.4 PCMCIA Connector (J4) The M3A-HS19 is provided with a PCMCIA connector (J4). Figure 3.1.5 shows the pin assignment for the PCMCIA connector (J4). 68 34 Top view of the solder side 35 1 J4 3.3V PCMCIA ONLY Board Edge Figure 3.1.5 Pin assignment for PCMCIA Connector (J4) Rev.1.01 Oct.28.
Operational Specifications 3 3.1.4 PCMCIA Connector (J4) Table 3.1.4 lists the pin assignment for the PCMCIA connector (J4). Table 3.1.4 Pin assignment for PCMCIA Connector (J4) Pin no. Signal Name Pin no.
Operational Specifications 3 3.1.5 LAN Connector (J5) 3.1.5 LAN Connector (J5) The M3A-HS19 is provided with a LAN connector (J5). Figure 3.1.6 shows the pin assignment for the LAN connector (J5). Top view of the solder side Top view of the component side J5 8 6 4 2 7 5 3 1 7 5 3 1 8 6 4 2 Board Edge Board Edge Figure 3.1.6 Pin assignment for LAN Connector (J5) Table 3.1.5 lists the pin assignment for the LAN connector (J5). Table 3.1.5 Pin assignment for LAN Connector (J5) Pin no.
Operational Specifications 3 3.1.6 H-UDI Connector (J6) 3.1.6 H-UDI Connector (J6) The M3A-HS19 is provided with an H-UDI (J6) connector to connect the E10A-USB emulator. Figure 3.1.7 shows the pin assignment for the H-UDI connector (J6). Top view the component side J6 1 8 7 14 H-UDI Figure 3.1.7 Pin assignment for H-UDI Connector (J6) Table 3.1.6 lists the pin assignment for the H-UDI connector (J6). Table 3.1.6 Pin assignment for H-UDI Connector (J6) Pin no. Signal Name Pin no.
Operational Specifications 3 3.1.7 Power Supply Connector (J7) 3.1.7 Power Supply Connector (J7) The M3A-HS19 is provided with a connector for power supply. Figure 3.1.8 shows the pin assignment for the power supply connector (J7). Top view of the component side Board Edge J7 Board Edge Side view Figure 3.1.8 Pin assignment for Power Supply Connector (J7) Table 3.1.7 lists the pin assignment for the power supply connector (J7). Table 3.1.7 Pin assignment for Power Supply Connector (J7) Pin no.
Operational Specifications 3 3.1.8 External Power Supply Connector (J8) 3.1.8 External Power Supply Connector (J8) The M3A-HS19 is provided with a through-hole for the SH7619 external power supply connector (J8: Supplies 1.8 V). Figure 3.1.9 shows the pin assignment for the external power supply connector (J8). Top view of the component side Top view of the solder side 1 2 1 2 J8 Board Edge Board Edge Figure 3.1.9 Pin assignment for External Power Supply Connector (J8) Table 3.1.
Operational Specifications 3 3.1.9 Expansion Connectors (J9-J13) 3.1.9 Expansion Connectors (J9-J13) The M3A-HS19 is provided with through-holes for expansion connectors. The Through-holes are connected to the SH7619 I/O pins. Expansion connectors (J9 - J13) can be connected to the MIL STD connector to mount expansion boards or to monitor the SH7619 bus signals. Figure 3.1.10 shows the pin assignment for expansion connectors. Figure 3.1.10 Pin assignment for Expansion Connectors Table 3.1.
Operational Specifications 3 3.1.9 Expansion Connectors (J9-J13) Table 3.1.10 Pin assignment for Expansion Connector (J10) Pin no. Signal Name Pin no. Signal Name 1 +3.3 V 2 +3.
Operational Specifications 3 3.1.9 Expansion Connectors (J9-J13) Table 3.1.12 Pin assignment for Expansion Connector (J12) Pin no. Signal Name Pin no. Signal Name 1 +5 V 2 +5 V 3 RD# 4 DD15 5 DD14 6 DD13 DD12 8 DD11 DD10 10 DD9 DD7 7 9 11 DD8 12 13 DD6 14 DD5 15 DD4 16 DD3 17 DD2 18 DD1 19 DD0 20 GND Table 3.1.13 Pin assignment for Expansion Connector (J11) Pin no. Signal Name Pin no.
Operational Specifications 3 3.2 Switches and LEDs 3.2 Switches and LEDs The M3A-HS19 is provided with switches and LEDs as its operational components. Figure 3.2.1 shows the assignment of operational components. Top view of the component side SW1 Power switch JP4 JP5 LED5 Power LED JP2 JP1 LED1-4 User LED JP9 Power switching jumper JP8 JP7 JP6 SW6 IRQ0 switch SW5 NMI switch SW2 Reset switch JP3 SW4 Mode Dip switch SW3 User Dip switch Figure 3.2.
Operational Specifications 3 3.2.1 Jumpers (JP1 - JP9) 3.2.1 Jumpers (JP1 - JP9) The M3A-HS19 is provided with nine jumpers. Figure 3.2.2 shows the jumper assignments (JP1 - JP9), and Table 3.2.1 through Table 3.2.6 list the jumper settings (JP1 - JP9). Figure 3.2.2 M3A-HS19 Jumpers Assignments (JP1 - JP9) Rev.1.01 Oct.28.
Operational Specifications 3 3.2.1 Jumpers (JP1 - JP9) Table 3.2.1 M3A-HS19 Jumper Settings (JP1) Jumper no. Setting Description JP1 1-2 PW EN PCMCIAPWSEL 2-3 PW PIO Table 3.2.2 M3A-HS19 Jumper Settings (JP2) Jumper no. Setting Description JP2 1-2 BUF OE PCMCIABUFOE 2-3 BUF PIO Table 3.2.3 M3A-HS19 Jumper Settings (JP3) Jumper no. Setting Description JP3 1-2 1.
Operational Specifications 3 3.2.2 Features of Switches and LED 3.2.2 Features of Switches and LEDs The M3A-HS19 is provided with six switches and five LEDs. Figure 3.2.3 shows the pin assignment for switches and LEDs. Table 3.2.7 lists the switches mounted on the M3A-HS19.
Operational Specifications 3 3.2.2 Features of Switches and LED Table 3.2.8 lists the SW4 features. Indicates the default setting. Table 3.2.8 SW4 Features No.
Operational Specifications 3 3.3 Dimensions 3.3 Dimensions Figure 3.3.1 shows the M3A-HS19 dimensions. Connectors can be mounted on J9 through J13 to simplify to mount an expansion board. Figure 3.3.1 M3A-HS19 Dimensions Rev.1.01 Oct.28.
Appendix M3A-HS19 SCHEMATICS A-1
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1 2 3 4 5 SH-2 SH7619 CPU BOARD M3A-HS19 Rev.C SCHEMATICS A A B TITLE PAGE INDEX CPU SH7619 FLASH MEMORY/SDRAM/EEPROM UART/ETHER/PCMCIA H-UDI/RESET/POWER BUS CONNECTORS/PUSH SW OTHERS 1 2 3 4 5 6 7 B Note: VCC = 5V 3VCC = 3.3V 1.8VCC = 1.8V C R RA C CE CP [Note] D = = = = = C Fixed Resistors Resistor Array Ceramic Caps Tantalum Electrolytic Caps Decoupling Caps :not mounted CHANGE RENESAS SOLUTIONS CORPORATION DRAWN SCALE Ver.1.
1 2 3 4 3AVCC R1 [4,5] MD5 [6] NMI [6] PD0/IRQ0/-/TEND0 3VCC R11 R12 4.7KΩ 4.7KΩ R17 12.4KΩ[1%] CK_PHY R127 4.7KΩ CS4 R128 4.
1 2 3 4 5 SDRAM FLASH MEMORY A A [2,4,6] DD[0:15] [2,4,6] A[0:25] SVDD FLASH CSC CHANNEL 0 16bit access = 4MB H3 SVDD 3VCC R19 SVDDQ 1 H4 SVDDQ 1 3VCC 0Ω R20 0Ω [2,6] _CS0 [2,4,6] _RD [2,6] _WE0/DQMLL CE OE WE 14 WP R27 4.7KΩ 3VCC R28 4.7KΩ R30 4.7KΩ FVDD [2,4,5,6] _WE0/DQMLL [5] FLASH_WP VDD VDD VDD VDDQ VDDQ VDDQ VDDQ DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 3VCC R23 4.
1 2 3 SERIAL CONNECTOR(RS232C) A R37 R39 R40 R41 R42 R43 RxD0 TxD0 RXD0 RXD2 TXD0 TXD2 R45 R48 R46 R47 0Ω 0Ω 0Ω 0Ω 3VCC C4 0.1µF [2,3,5,6] R124 _RES R123 4.7KΩ 0Ω 5 9 4 8 3 7 2 6 1 RS-232 R1OUT R2OUT T1IN T2IN 2 C1+ 4 5 C1C2+ 6 C2- 16 9 17 8 R1IN R2IN T1OUT T2OUT TxD2 RxD2 V+ 3 C2 V- 7 C3 U5 2 3 4 EN1 EN0 HW-3P 6 7 3VIN 3VIN 2 5VIN 3 0.1µF 0.1µF EN SHDN CP28 0.1µF 18 GND Hot-Plug buffer J3 1 2 3 4 Decoupling Caps 3VCC A2-4PA-2.
1 2 3 4 5 H-UDI INTERFACE 3VCC 5 10 3VCC RA7 A4.7KΩ 1 2 3 4 6 7 8 9 5V TO 3.3V LINEAR REGULATOR 1-2 Power On 2-3 Power Off [2] TMS [2] TDI 8 11 R69 1KΩ TCK (GND) _TRST GND TDO N.C. TMS GND TDI GND _RESET GND 9 10 J14 HEC0470-01-630 1 3 2 _ASEMD [2] 12 13 14 JP9 SW1 2 1 3 2 XG8V-0334 3VCC U12 LMS1587CS-ADJ 3 IN 1 3 MS-12AAH1 Power Connector N.C. UVCC A VCC + CE4 10µF ADJ/GND J6 1 2 3 4 5 6 7 [2] TCK [2] _TRST [2] TDO Power Switch OUT TAB 2 4 Vout = 3.
1 2 3 4 5 Extension Bus Connector 3VCC [2,3,4] A[0:25] A PE18/HIFD09/TXD1 A23 PA23/RXD_SIO0 J9 [5] _RESET_IN [2,4] PB00/_WAIT [2,4] PB13/_BS [2,4] PA25/SIOFSYNC0 [2,3] PC01/MII_RXD1 [2,4] PD3/IRQ3/RXD1/DACK0 [2,3] PC00/MII_RXD0 [2,4] PD2/IRQ2/TXD1/DREQ0 [2,3] PC03/MII_RXD3 [2] PE07/HIFRS [2,3] PC02/MII_RXD2 [2] PE01/HIFRDY [2,4] PC20/WOL PB00/_WAIT PA25/SIOFSYNC0 PE07/_HIFRS [2,4] PC15/CRS [2] PE04/_HIFINT R97 0Ω R94 0Ω R91 0Ω R90 0Ω R93 0Ω R92 0Ω R95 0Ω R96 0Ω JP4 1 R88 R89
1 2 3 4 5 TEST PIN VCC A 3VCC MH1 1.8VCC A H10 H11 H12 H13 1 1 1 1 VCC 3VCC 1.8VCC GND J15 1 2 3 1 1 XG8S-0331 MOUNT-HOLE AGND-GND MH2 L1 1 1 BLM18PG330SN1 B B MOUNT-HOLE MH3 VCC 1 1 CQ1 0.1µF CQ2 0.1µF CQ3 0.1µF CQ5 0.1µF CQ12 0.1µF CQ13 0.1µF MOUNT-HOLE MH4 3VCC C CQ4 0.1µF CQ6 0.1µF CQ7 0.1µF CQ9 0.1µF CQ10 0.1µF C 1 1 CQ11 0.1µF MOUNT-HOLE PCVCC CQ8 0.1µF D CHANGE RENESAS SOLUTIONS CORPORATION DRAWN SCALE Ver.1.
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Revision History Rev. SH7619 CPU Board M3A-HS19User's Manual Date Description Page Summary 1.00 Aug 28, 2008 - First edition issued. 1.01 Oct 28, 2008 - Errors corrected.
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SH7619 CPU Board M3A-HS19 User's Manual Publication Date Oct 28, 2008 Rev. 1.01 Published by Renesas Technology Corp. Renesas Solutions Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
M3A-HS19 User's Manual