Datasheet

M32C/8B Group 1. Overview
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 8 of 67
1.4 Pin Assignments
Figures 1.3 and 1.4 show pin assignments (top view).
Figure 1.3 Pin Assignment for 144-pin Package
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
M32C/8B Group
PLQP0144KA-A
(144P6Q-A)
(top view)
<VCC2>
<VCC1>
ANEX1 / TXD4 / SDA4 / SRXD4 / P9_6
ANEX0 / CLK4 / P9_5
DA1 / SS4 / RTS4 / CTS4 / TB4IN / P9_4 DA0 / SS3 / RTS3 / CTS3 / TB3IN / P9_3
SRXD3 / SDA3 / TXD3 / TB2IN / P9_2
STXD3 / SCL3 / RXD3 / TB1IN / P9_1
CLK3 / TB0IN / P9_0
P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0
BYTE
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC1
NMI / P8_5
INT2 / P8_4 INT1 / P8_3 INT0 / P8_2
U / TA4IN / P8_1
U / TA4OUT / P8_0
TA3IN / P7_7
TA3OUT / P7_6
W / TA2IN / P7_5
W / TA2OUT / P7_4
SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
CLK2 / V / TA1OUT / P7_2
(1) STXD2 / SCL2 / RXD2 / TB5IN / TA0IN / P7_1 P4_3 / A19
VCC2 P4_2 / A18 P4_1 / A17 P4_0 / A16 VSS P3_7 / A15 , [ A15 / D15 ] P3_6 / A14 , [ A14 / D14 ] P3_5 / A13 , [ A13 / D13 ] P3_4 / A12 , [ A12 / D12 ] P3_3 / A11 , [ A11 / D11 ] P3_2 / A10 , [ A10 / D10 ]
P
3
_
1
/
A
9
,
[
A
9
/
D
9
]
P
3
_
0
/
A
8
,
[
A
8
/
D
8
]
P
2
_
7
/
A
N
2
_
7
/
A
7
,
[
A
7
/
D
7
]
V
S
S
V
C
C
2
P
1
2
_
0
P
1
2
_
1
P
1
2
_
2
P
1
2
_
3
P
1
2
_
4
P
1
_
5
/
I
N
T
3
/
D
1
3
P
1
_
6
/
I
N
T
4
/
D
1
4
P
1
_
7
/
I
N
T
5
/
D
1
5
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 (1)
P6_7 / TXD1 / SDA1 / SRXD1
VCC1
P6_6 / RXD1 / SCL1 / STXD1
VSS
P6_5 / CLK1
P
6
_
4
/
C
T
S
1
/
R
T
S
1
/
S
S 1
P
6
_
3
/
T
X
D
0
/
S
D
A
0
/
S
R
X
D
0
P
6
_
2
/
R
X
D
0
/
S
C
L
0
/
S
T
X
D
0
P6_1 / CLK0
P6_0 / CTS0 / RTS0 / SS0
P13_7
P13_6
P13_5
P13_4
P5_7 / RDY
P5_6 / ALE
P5_5 / HOLD
P5_4 / HLDA / ALE
P13_3
VSS
P13_2
VCC2
P13_1
P13_0
P5_3 / CLKOUT / BCLK / ALE
P5_2 / RD
P5_1/WRH/BHE
P5_0 / WRL / WR
P12_7
P12_6
P12_5
P4_7 / CS0 / A23
P4_6 / CS1 / A22
P4_5 / CS2 / A21
P4_4 / CS3 / A20
D8 / P1_0
D7 / AN0_7 / P0_7
D6 / AN0_6 / P0_6
D5 / AN0_5 / P0_5
D4 / AN0_4 / P0_4
P11_4
P11_3
P11_2
P11_1
P11_0
D3 / AN0_3 / P0_3
D2 / AN0_2 / P0_2
D1 / AN0_1 / P0_1
D0 / AN0_0 / P0_0
AN15_7 / P15_7
AN15_6 / P15_6
AN15_5 / P15_5
AN15_4 / P15_4
AN15_3 / P15_3
AN15_2 / P15_2
AN15_1 / P15_1
AN15_0 / P15_0
VSS
VCC1
AN_7 / KI3 / P10_7
AN_6 / KI2 / P10_6
AN_5 / KI1 / P10_5
AN_4 / KI0 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AN_0 / P10_0
AVSS
AVCC
VREF
A
D
T
R
G
/
S
T
X
D
4
/
S
C
L
4
/
R
X
D
4
/
P
9
_
7
NOTES:
1. P7_0 and P7_1 are N-channel open drain output ports .
2. Refer to Package Dimensions for the pin1 position on the package.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
P
1
_
1
/
D
9
P
1
_
2
/
D
1
0
P
1
_
3
/
D
1
1
P
1
_
4
/
D
1
2
P
2
_
6
/
A
N
2
_
6
/
A
6
,
[
A
6
/
D
6
]
P
2
_
5
/
A
N
2
_
5
/
A
5
,
[
A
5
/
D
5
]
P
2
_
4
/
A
N
2
_
4
/
A
4
,
[
A
4
/
D
4
]
P
2
_
3
/
A
N
2
_
3
/
A
3
,
[
A
3
/
D
3
]
P
2
_
2
/
A
N
2
_
2
/
A
2
,
[
A
2
/
D
2
]
P
2
_
1
/
A
N
2
_
1
/
A
1
,
[
A
1
/
D
1
]
P
2
_
0
/
A
N
2
_
0
/
A
0
,
[
A
0
/
D
0
]
( note 3 )
( note 2 )