Datasheet

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1. Overview
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 9 of 85
1.4 Pin Assignments
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M32C/87 Group
(M32C/87, M32C/87A, M32C/87B)
PLQP0144KA-A
(144P6Q-A)
(top view)
<VCC2>
<VCC1>
D8 / P1_0
D7 / AN0_7 / P0_7
D6 / AN0_6 / P0_6
D5 / AN0_5 / P0_5
D4 / AN0_4 / P0_4
P11_4
OUTC1_3 / INPC1_3 / P11_3
ISRXD1 / OUTC1_2 / INPC1_2 / P11_2
ISCLK1 / OUTC1_1 / INPC1_1 / P11_1
ISTXD1 / OUTC1_0 / INPC1_0 / P11_0
D3 / AN0_3 / P0_3
D2 / AN0_2 / P0_2
D1 / AN0_1 / P0_1
D0 / AN0_0 / P0_0
AN15_7 / RTS6 / CTS6 / P15_7
AN15_6 / CLK6 / P15_6
AN15_5 / RXD6 / P15_5
AN15_4 / TXD6 / P15_4
AN15_3 / RTS5 / CTS5 / P15_3
AN15_2 / ISRXD0 / RXD5 / P15_2
AN15_1 / ISCLK0 / CLK5 / P15_1
AN15_0 / ISTXD0 / TXD5 / P15_0
VSS
VCC1
AN_7 / RTP3_3 / KI3 / P10_7
AN_6 / RTP3_2 / KI2 / P10_6
AN_5 / RTP3_1 / KI1 / P10_5
AN_3 / RTP1_3 / P10_3
AN_2 / RTP1_2 / P10_2
AN_1 / RTP1_1 / P10_1
AN_0 / RTP1_0 / P10_0
AVSS
AVCC
VREF
ADTRG / STXD4 / SCL4 / RXD4 / P9_7
(5)
ANEX1 / SRXD4 / SDA4 / TXD4 / CAN1OUT / P9_6
(5)
ANEX0 / CAN1WU / CAN1IN / CLK4 / P9_5
DA1 / SS4 / RTS4 / CTS4 / TB4IN / P9_4 DA0 / SS3 / RTS3 / CTS3 / TB3IN / P9_3
ISTXD2 / IEOUT / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN / P9_2
ISRXD2 / IEIN / STXD3 / SCL3 / RXD3 / TB1IN / P9_1
CLK3 / TB0IN / P9_0
INT8 / P14_6 INT7 / P14_5 INT6 / P14_4
OUTC1_7 / INPC1_7 / P14_3 OUTC1_6 / INPC1_6 / P14_2 OUTC1_5 / INPC1_5 / P14_1 OUTC1_4 / INPC1_4 / P14_0
BYTE
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC1
NMI / P8_5
INT2 / P8_4
(5)
CAN1IN / CAN0IN / INT1 / P8_3
(5)
CAN1OUT / CAN0OUT / INT0 / P8_2
OUTC1_5 / INPC1_5 / RTS5 / CTS5 / RTP2_3 / U / TA4IN / P8_1
ISRXD0 / RXD5 / U / TA4OUT / P8_0
ISCLK0 / OUTC1_4 / INPC1_4 / CAN0IN / CLK5 / RTP2_2 / TA3IN / P7_7
ISTXD0 / OUTC1_3 / INPC1_3 / TXD5 / CAN0OUT / TA3OUT / P7_6
ISRXD0 / OUTC1_2 / INPC1_2 / RTP2_1 / W / TA2IN / P7_5
ISCLK1 / OUTC1_1 / INPC1_1 / RTP2_0 / W / TA2OUT / P7_4
I
S
T
X
D
1
/
O
U
T
C
1
_
0
/
I
N
P
C
1
_
0
/
S
S
2
/
R
T
S
2
/
C
T
S
2
/
V
/
T
A
1
I
N
/
P
7
_
3
CLK2 / V / TA1OUT / P7_2
(1) (4)
P7_1 P4_3 / A19
VCC2 P4_2 / A18 P4_1 / A17 P4_0 / A16 VSS P3_7 / A15, [A15/D15] P3_6/ A14, [A14/D14] P3_5/ A13, [A13/D13] P3_4 / A12, [A12/D12] P3_3 / A11, [A11/D11] P3_2 / A10, [A10/D10]
P
3
_
1
/
A
9
,
[
A
9
/
D
9
]
P3_0/ A8, [A
8/D8]
(7)
P
2
_
7
/
A
N
2
_
7
/
A
7
,
[
A
7
/
D
7
]
P
2
_
6
/
A
N
2
_
6
/
A
6
,
[
A
6
/
D
6
]
P
2
_
5
/
A
N
2
_
5
/
A
5
,
[
A
5
/
D
5
]
P
2
_
4
/
A
N
2
_
4
/
A
4
,
[
A
4
/
D
4
]
V
S
S
V
C
C
2
P
1
2
_
0
/
T
X
D
6
P
1
2
_
1
/
C
L
K
6
P
1
2
_
2
/
R
X
D
6
P
1
2
_
3
/
C
T
S
6
/
R
T
S
6
P
1
2
_
4
P
2
_
3
/
A
N
2
_
3
/
A
3
,
[
A
3
/
D
3
]
P
2
_
2
/
A
N
2
_
2
/
A
2
,
[
A
2
/
D
2
]
P
2
_
1
/
A
N
2
_
1
/
A
1
,
[
A
1
/
D
1
]
P
2
_
0
/
A
N
2
_
0
/
A
0
,
[
A
0
/
D
0
]
P
1
_
1
/
D
9
P
1
_
2
/
D
1
0
P
1
_
3
/
D
1
1
P
1
_
4
/
D
1
2
P
1
_
5
/
I
N
T
3
/
D
1
3
P
1
_
6
/
I
N
T
4
/
D
1
4
P
1
_
7
/
I
N
T
5
/
D
1
5
P7_0
(2) (4)
P6_7 / TXD1 / SDA1 / SRXD1
VCC1
P6_6 / RXD1 / SCL1 / STXD1
VSS
P6_5 / CLK1
P6_4
(3)
P6_3 / TXD0 / SDA0 / SRXD0 / IrDAOUT
P6_2 / RXD0 / SCL0 / STXD0 / IrDAIN
P6_1 / RTP0_1 / CLK0
P6_0 / RTP0_0 / CTS0 / RTS0 / SS0
P13_7 / OUTC2_7
P13_6 / OUTC2_1 / ISCLK2
P13_5 / OUTC2_2 / ISRXD2 / IEIN
P13_4 / OUTC2_0 / ISTXD2 / IEOUT
P5_7 / RDY
P5_6 / ALE
P5_5 / HOLD
P5_4 / HLDA / ALE
P13_3 / OUTC2_3
VSS
P13_2 / OUTC2_6
VCC2
P13_1 / OUTC2_5
P13_0 / OUTC2_4
P5_3 / CLKOUT / BCLK / ALE
P5_2 / RD
P5_1 / WRH / BHE
P5_0 / WRL / WR
P12_7
P12_6
P12_5
P4_7 / CS0 / A23
P4_6 / CS1 / A22
P4_5 / CS2 / A21
P4_4 / CS3 / A20
AN_4 / RTP3_0 / KI0 / P10_4
NOTES:
1. P7_1 / TA0IN / TB5IN / RTP0_3 / RXD2 / SCL2 / STXD2 / INPC1_7 / OUTC1_7 / OUTC2_2 / ISRXD2 / IEIN
2. P7_0 / TA0OUT / RTP0_2 / TXD2 / SDA2 / SRXD2 / INPC1_6 / OUTC1_6 / OUTC2_0 / ISTXD2 / IEOUT
3. P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
4. P7_0 and P7_1 are N-channel open drain output ports.
5. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A.
6. Refer to Package Dimensions for the pin1 position on the package.
7. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
(note 6)
( note 7)
( note 7)
Figures 1.3 to 1.5 show pin assignments (top view).
Figure 1.3 Pin Assignment for 144-Pin Package