Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16/32-Bit 32 MHz I/O number 85

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (93 pages)

PAGE 1
To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) RENESAS MCU 1. REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Overview 1.1 Features The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) is a single-chip control MCU, fabricated using highperformance silicon gate CMOS technology, embedding the M32C/80 Series CPU core. The M32C/87 Group (M32C/ 87, M32C/87A, M32C/87B) is housed in 144-pin and 100-pin plastic molded LQFP/QFP packages.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.1.2 1. Overview Specifications Tables 1.1 to 1.4 list the specifications of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). Table 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.2 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.3 Item CPU Specifications (100-Pin Package) (1/2) Function Central processing unit Memory ROM, RAM, data flash Power Supply Voltage Detection External Bus Expansion Bus/memory expansion function Clock Clock generation circuits Interrupts Watchdog Timer DMA DMAC DMACII Timer 1. Overview Timer A Timer B Timer function for 3-phase motor control REJ03B0127-0151 Rev.1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.4 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.2 1. Overview Product List Tables 1.5 to 1.7 list product information. Figure 1.1 shows product numbering system. Table 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.7 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.3 1. Overview Block Diagram Figure 1.2 shows a block diagram of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.4 1. Overview Pin Assignments Figures 1.3 to 1.5 show pin assignments (top view).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.8 Pin No. Control Pin 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.9 Pin No. Control Pin 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.10 Pin No. Control Pin 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.11 Pin No. Control Pin 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.12 Pin No. FP GP 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.13 Pin No. FP GP 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.14 Pin No. FP GP 73 71 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.5 1. Overview Pin Functions Table 1.15 Type Pin Functions (100-Pin and 144-Pin Packages) (1/4) Symbol I/O Supply Description Type Voltage − − Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin. The input condition of VCC1 ≥ VCC2 must be met. − VCC1 Power supply input pins to the A/D converter and D/A converter. Connect the AVCC pin to VCC1, and the AVSS pin to VSS.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.16 Pin Functions (100-Pin and 144-Pin Packages) (2/4) Type Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input NMI interrupt input Timer A Timer B Three-phase motor control timer output Serial interface I2C mode Symbol XIN XOUT CAN(1) I/O Supply Description Type Voltage I VCC1 Input/output pins for the main clock oscillation circuit.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.17 Type Intelligent I/O Pin Functions (100-Pin and 144-Pin Package) (3/4) Symbol INPC1_0 to INPC1_3 INPC1_4 to INPC1_7 OUTC1_0 to OUTC1_3 OUTC1_4 to OUTC1_7 OUTC2_0 to OUTC2_2 ISCLK0 ISCLK1, ISCLK2 ISRXD0 ISRXD1, ISRXD2 ISTXD0 ISTXD1, ISTXD2 IEIN Reference voltage input A/D converter 1. Overview I/O Supply Description Type Voltage I VCC1/ Input pins for the time measurement function.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.18 Type I/O port Input port Key input interrupt input I: Input Pin Functions (100-Pin and 144-Pin Package) (4/4) I/O Supply Description Type Voltage P0_0 to P0_7, I/O VCC2 8-bit CMOS I/O ports. The Port Pi Direction Register (i = 0 to 15) P1_0 to P1_7, determines if each pin is used as an input port or an output port. P2_0 to P2_7, The Pull-Up Control Registers determine if the input ports, divided P3_0 to P3_7, into groups of four, are pulled up or not.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There are two sets of register banks.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 2.1 2. Central Processing Unit (CPU) General Registers 2.1.1 Data Registers (R0, R1, R2, and R3) R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1. 2.1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 2.1.8.7 2. Central Processing Unit (CPU) Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when an interrupt request is acknowledged. 2.1.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 3. 3. Memory Memory Figure 3.1 shows a memory map of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has 16-Mbyte address space from addresses 000000h to FFFFFFh. The internal ROM is allocated in lower addresses, beginning with address FFFFFFh. For example, a 512-Kbyte internal ROM area is allocated in addresses F80000h to FFFFFFh. The fixed interrupt vectors are allocated in addresses FFFFDCh to FFFFFFh.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 4. 4. Special Function Registers (SFRs) Special Function Registers (SFRs) Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.20 list SFR address maps. Table 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.2 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.3 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.4 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.5 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.6 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.7 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.8 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.9 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.10 SFR Address Map (10/20) Register(3)(4) Address 0220h 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.11 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.12 SFR Address Map (12/20) Register(3)(4) Address 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.13 Address 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.14 SFR Address Map (14/20) Address 02C0h 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.15 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.16 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.17 SFR Address Map (17/20) Address 0350h 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.18 SFR Address Map (18/20) Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.19 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.20 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. 5. Electrical Characteristics Electrical Characteristics Table 5.1 Absolute Maximum Ratings Symbol Parameter Condition Value Unit VCC1, VCC2 Supply voltage VCC1 = AVCC -0.3 to 6.0 V VCC2 Supply voltage − -0.3 to VCC1 + 0.1 V AVCC Analog supply voltage VCC1 = AVCC -0.3 to 6.0 V VI Input voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1), VREF, XIN -0.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 5.2 5. Electrical Characteristics Recommended Operating Conditions (1/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified) Symbol Parameter VCC1, VCC2 Supply voltage (VCC1 ≥ VCC2) AVCC Analog supply voltage Standard Min. Typ. Max. 3.0 5.0 5.5 Unit VCC1 V V VSS Supply voltage 0 V AVSS Analog supply voltage 0 V VIH 0.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 5.3 5. Electrical Characteristics Recommended Operating Conditions (2/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified Symbol Parameter Standard Min. Typ. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 5.4 Recommended Operating Conditions (3/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified) Symbol f(CPU) 5. Electrical Characteristics Standard Parameter Min. Typ. Max. Unit CPU clock frequency (same frequency as f(BCLK)) VCC1 = 4.2 to 5.5V 0 32 MHz VCC1 = 3.0 to 5.5V 0 24 MHz f(XIN) Main clock input oscillation frequency VCC1 = 4.2 to 5.5V 0 32 MHz VCC1 = 3.0 to 5.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Table 5.5 Electrical Characteristics (1/3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 32 MHz unless otherwise specified) VOH Min. P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) IOH = -5 mA VCC2 - 2.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Table 5.6 Electrical Characteristics (2/3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 32 MHz unless otherwise specified) Symbol Parameter Measurement Condition Standard Min. Typ. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Table 5.7 Electrical Characteristics (3/3) (VCC1 = VCC2 = 5.5 V, VSS = 0 V, Topr = 25°C) Measurement Condition(1) Symbol Parameter ICC Power supply current Flash memory version Standard Min. Typ. Max. f(CPU) = 32 MHz 32 f(CPU) = 16 MHz 19 mA f(CPU) = 8 MHz 12 mA f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode 2.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Table 5.8 A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85°C, f(CPU) = 32MHz unless otherwise specified) Symbol Parameter Measurement Condition − Resolution VREF = VCC1 INL Integral nonlinearity error VREF = VCC1 = VCC2 = 5 V Standard Min. Typ. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Table 5.10 Flash Memory Electrical Characteristics (VCC1 = 4.5 V to 5.5 V, 3.0 to 3.6 V, Topr = 0 to 60°C unless otherwise specified) Symbol Parameter Measurement Condition Standard Min. Typ. Max. Unit − Erase and program endurance(1) − Word program time (16 bits) (VCC1 = 5.0 V, Topr = 25°C) 25 300 μs − Lock bit program time 25 300 μs − Block erase time (VCC1 = 5.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Table 5.11 Voltage Detection Circuit Electrical Characteristics (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, Topr = 25°C unless otherwise specified) Symbol Parameter Measurement Condition Vdet4 Vdet4 detection voltage Vdet3 Vdet3 detection voltage Vdet3s Hardware reset 2 hold voltage Vdet3r Hardware reset 2 release voltage Standard Min. Typ. Max. 3.3 3.8 4.4 3.0 VCC1 = 3.0 V to 5.5 V Unit V V 2.0 3.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.13 External Clock Input Symbol Parameter Standard Min. Max. Unit tc External clock input cycle time 31.25 ns tw(H) External clock input high (“H”) pulse width 13.75 ns tw(L) External clock input low (“L”) pulse width 13.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.18 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.23 A/D Trigger Input Symbol Parameter Standard Min. Max. Unit tc(AD) ADTRG input cycle time (required for trigger) 1000 ns tw(ADL) ADTRG input low (“L”) pulse width 125 ns Table 5.24 Serial Interface Symbol Parameter Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.27 External Interrupt INTi Input (Edge Sensitive) Symbol tw(INH) tw(INL) Parameter Standard Min. Max. Unit INTi input high (“H”) pulse width 250 ns INTi input low (“L”) pulse width 250 ns i = 0 to 8(1) NOTE: 1. INT6 to INT8 are provided in the 144-pin package only. REJ03B0127-0151 Rev.1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.28 Memory Expansion mode and Microprocessor Mode Symbol Parameter Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.30 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space with multiplexed bus) Symbol Measurement Condition Parameter td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (BCLK standard) Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 30 pF Note 1 NOTE: 1. P11 to P15 are provided in the 144-pin package only. Figure 5.2 P0 to P15 Measurement Circuit REJ03B0127-0151 Rev.1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode and Microprocessor Mode BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY Input tsu(RDY-BCLK) th(BCLK-RDY) BCLK th(BCLK-HOLD) tsu(HOLD-BCLK) HOLD Input HLDA Output td(BCLK-HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 td(BCLK-HLDA) Hi-Z Measurement Conditions - VCC1 = VCC2 = 4.2 to 5.5 V - Input high and low voltage: VIH = 4.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) VCC1=VCC2=5V Read Timing (1φ + 1φ Bus Cycle) BCLK th(BCLK-CS) -3ns.min td(BCLK-CS) 18ns.max(1) CSi tcyc th(RD-CS) 0ns.min td(BCLK-AD) 18ns.max(1) th(BCLK-AD) -3ns.min ADi BHE td(BCLK-RD) th(RD-AD) 0ns.min 18ns.max RD th(BCLK-RD) -5ns.min tac1(RD-DB)(2) tac1(AD-DB)(2) DBi Hi-Z tsu(DB-BCLK) 26ns.min(1) th(RD-DB) 0ns.min NOTES: 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) VCC1=VCC2=5V Read Timing (2φ + 2φ Bus Cycle) BCLK td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min tcyc th(RD-CS)(1) CSi ADi /DBi tsu(DB-BCLK) 26ns.min th(ALE-AD)(1) td(AD-ALE)(1) Address Data input tdz(RD-AD) 8ns.max td(BCLK-AD) 18ns.max Address th(RD-DB) 0ns.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Table 5.31 Electrical Characteristics (1/3) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 24 MHz unless otherwise specified) Symbol VOH Parameter Output high “H” voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) Min. IOH = -1 mA VCC2 - 0.6 VCC2 VCC1 - 0.6 VCC1 2.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Table 5.32 Electrical Characteristics (2/3) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 24 MHz unless otherwise specified) Symbol Parameter Measurement Condition Standard Min. Typ. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Table 5.33 Electrical Characteristics (3/3) (VCC1 = VCC2 = 3.3 V, VSS = 0 V, Topr = 25°C) Measurement Condition(1) Symbol Parameter ICC Power supply current Flash memory version Standard Min. Typ. Max. f(CPU) = 24 MHz 23 f(CPU) = 16 MHz 17 mA f(CPU) = 8 MHz 11 mA f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode 2.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Table 5.34 A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85°C, f(CPU) = 24MHz unless otherwise specified) Symbol Parameter Measurement Condition Standard Min. Typ. Max. Unit − Resolution VREF = VCC1 10 Bits INL Integral nonlinearity error (8-bit) VREF = VCC1 = VCC2 = 3.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.36 External Clock Input Symbol Parameter Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.41 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.46 A/D Trigger Input Symbol Parameter Standard Min. Max. Unit tc(AD) ADTRG input cycle time (required for trigger) 1000 ns tw(ADL) ADTRG input low (“L”) pulse width 125 ns Table 5.47 Serial Interface Symbol Parameter Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.50 External Interrupt INTi Input (Edge Sensitive) Symbol tw(INH) tw(INL) Parameter Standard Min. Max. Unit INTi input high (“H”) pulse width 250 ns INTi input low (“L”) pulse width 250 ns i = 0 to 8(1) NOTE: 1. INT6 to INT8 are provided in the 144-pin package only. REJ03B0127-0151 Rev.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.51 Memory Expansion Mode and Microprocessor Mode Symbol Parameter Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1 = VCC2 = 3.3 V Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified) Table 5.53 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space with multiplexed bus) Symbol Measurement Condition Parameter td(BCLK-AD) Address output delay time th(BCLK-AD) Address output hold time (BCLK standard) Standard Min. Max.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1=VCC2=3.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics VCC1=VCC2=3.3V Memory Expansion Mode and Microprocessor Mode BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY Input tsu(RDY-BCLK) th(BCLK-RDY) BCLK th(BCLK-HOLD) tsu(HOLD-BCLK) HOLD Input HLDA Output td(BCLK-HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 td(BCLK-HLDA) Hi-Z Measurement Conditions -VCC1 = VCC2 = 3.0 to 3.6 V -Input high and low voltage: VIH = 2.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) VCC1=VCC2=3.3V Read Timing (1φ + 1φ Bus Cycle) BCLK th(BCLK-CS) -3ns.min td(BCLK-CS) 18ns.max(1) CSi tcyc th(RD-CS) 0ns.min td(BCLK-AD) 18ns.max(1) th(BCLK-AD) -3ns.min ADi BHE td(BCLK-RD) th(RD-AD) 0ns.min 18ns.max RD th(BCLK-RD) -5ns.min tac1(RD-DB)(2) tac1(AD-DB)(2) DBi Hi-Z tsu(DB-BCLK) 30ns.min(1) th(RD-DB) 0ns.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) VCC1=VCC2=3.3V Read Timing (2φ + 2φ Bus Cycle) BCLK td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min ALE td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min tcyc th(RD-CS)(1) CSi ADi /DBi tsu(DB-BCLK) 30ns.min th(ALE-AD)(1) td(AD-ALE)(1) Address Data input tdz(RD-AD) 8ns.max td(BCLK-AD) 18ns.max Address th(RD-DB) 0ns.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JB-A Previous Code 100P6S-A Appendix 1. Package Dimensions MASS[Typ.] 1.6g HD *1 D 80 51 81 50 E *2 HE NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. ZE Reference Dimension in Millimeters Symbol 100 31 30 c F A2 Index mark ZD A1 A 1 L *3 e y bp REJ03B0127-0151 Rev.1.
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REVISION HISTORY M32C/87 Group Datasheet Description Rev. Date 0.50 Dec.16, 04 − New Document 1.00 Jul.14, 05 − − M32C/87A and M32C/87B added Package code changed: 144P6Q-A to PLQP0144KA-A, 100P6Q-A to PLQP0100KB-A, 100P6S-A to PRQP0100JB-A “Low Voltage Detection Reset” changed to “Brown-out Detection Reset” Page − Summary 4 7 8 11 12 13 17 Overview • Table 1.
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REVISION HISTORY Rev. Date Description Page 57 58 60 61 62 64 65 66 69 70 71 72 73 1.01 M32C/87 Group Datasheet Aug. 29, 05 Summary Electrical Characteristics • Table 5.22 Memory Expansion Mode and Microprocessor Mode th(WRDB) expression on note 1 modified • Table 5.23 Memory Expansion Mode and Microprocessor Mode th(WRDB) expression on note 1 modified; th(ALE-AD) expression on note 4 modified • Figure 5.
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REVISION HISTORY Rev. Date 1.50 Oct 20, 2007 M32C/87 Group Datasheet Description Page All Summary All in this manual • Descriptions and formats unified • Notation of numbers changed (e.g. 002 → 00b, FF16 → FFh) • Notation of pin name changed (e.g.
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REVISION HISTORY Rev. Date Description Page 42 27 27 29 31 31 32 34 34 44 47 50-53 50 51,69 53,71 54 54,55 56,73 58,74 59 60 61 62-63 65-68 69-72 75 76 77 78-79 80-83 1.
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REVISION HISTORY Rev. Date M32C/87 Group Datasheet Description Page 46 Summary Special Function Registers (SFRs) • Table 4.20 A value of After Reset column in 03FFh modified All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use.