Datasheet

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 79 of 85
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.53 Memory Expansion Mode and Microprocessor Mode
(when accessing external
memory space with multiplexed bus)
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
10
9
f(BCLK) × 2
- 10 [ns]
th(RD-AD) =
10
9
f(BCLK) × 2
- 15 [ns]
th(WR-AD) =
10
9
f(BCLK) × 2
- 10 [ns]
th(RD-CS) =
10
9
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
10
9
f(BCLK) × 2
- 20 [ns]
th(WR-DB) =
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
10
9
× m
f(BCLK) × 2
- 25 [ns] (if external bus cycle is a
φ + bφ, m = (b × 2) - 1)
td(DB-WR) =
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
10
9
× n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is a
φ + bφ, n = a)
td(AD-ALE) =
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
10
9
× n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is a
φ + bφ, n = a)
th(ALE-AD) =
5. tc [ns] is added when recovery cycle is inserted.
Symbol Parameter
Measurement
Condition
Standard
Unit
Min. Max.
td(BCLK-AD)
Address output delay time
See Figure 5.2
18
ns
th(BCLK-AD)
Address output hold time (BCLK standard) -3
ns
th(RD-AD)
Address output hold time (RD standard)
(5)
(note 1)
ns
th(WR-AD)
Address output hold time (WR standard)
(5)
(note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time 18
ns
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard) -3
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)
(5)
(note 1)
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)
(5)
(note 1)
ns
td(BCLK-RD)
RD signal output delay time 18
ns
th(BCLK-RD)
RD signal output hold time -5
ns
td(BCLK-WR)
WR signal output delay time 18
ns
th(BCLK-WR)
WR signal output hold time 0
ns
td(DB-WR)
Data output delay time (WR standard) (note 2)
ns
th(WR-DB)
Data output hold time (WR standard)
(5)
(note 1)
ns
td(BCLK-ALE)
ALE signal output delay time (BCLK standard) 18
ns
th(BCLK-ALE)
ALE signal output hold time (BCLK standard) -2
ns
td(AD-ALE)
ALE signal output delay time (address standard) (note 3)
ns
th(ALE-AD)
ALE signal output hold time (address standard) (note 4)
ns
tdz(RD-AD)
Address output float start time 8
ns
VCC1 = VCC2 = 3.3 V