Datasheet

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 75 of 85
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.46 A/D Trigger Input
Table 5.47 Serial Interface
i = 0 to 6
Table 5.48 Intelligent I/O Communication Function (Groups 0 and 1)
i = 0, 1
Table 5.49 Intelligent I/O Communication Function (Group 2)
Symbol Parameter
Standard
Unit
Min. Max.
tc(AD)
ADTRG
input cycle time (required for trigger)
1000 ns
tw(ADL)
ADTRG
input low (“L”) pulse width
125 ns
Symbol Parameter
Standard
Unit
Min. Max.
tc(CK) CLKi input cycle time 200 ns
tw(CKH) CLKi input high (“H”) pulse width 100 ns
tw(CKL) CLKi input low (“L”) pulse width 100 ns
td(C-Q) TXDi output delay time 80 ns
th(C-Q) TXDi output hold time 0 ns
tsu(D-C) RXDi input setup time 70 ns
th(C-D) RXDi input hold time 90 ns
Symbol Parameter
Standard
Unit
Min. Max.
tc(CK) ISCLKi input cycle time 600 ns
tw(CKH) ISCLKi input high (“H”) pulse width 300 ns
tw(CKL) ISCLKi input low (“L”) pulse width 300 ns
td(C-Q) ISTXDi output delay time 100 ns
th(C-Q) ISTXDi output hold time 0 ns
tsu(D-C) ISRXDi input setup time 100 ns
th(C-D) ISRXDi input hold time 100 ns
Symbol Parameter
Standard
Unit
Min. Max.
tc(CK) ISCLK2 input cycle time 600 ns
tw(CKH) ISCLK2 input high (“H”) pulse width 300 ns
tw(CKL) ISCLK2 input low (“L”) pulse width 300 ns
td(C-Q) ISTXD2 output delay time 180 ns
th(C-Q) ISTXD2 output hold time 0 ns
tsu(D-C) ISRXD2 input setup time 150 ns
th(C-D) ISRXD2 input hold time 100 ns
VCC1 = VCC2 = 3.3 V