Datasheet

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Electrical Characteristics
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 65 of 85
Figure 5.3 VCC1 = VCC2 = 5 V Timing Diagram (1/4)
VCC1=VCC2=5V
TAiIN input
tc(TA)
tw(TAH)
tw(TAL)
TAiOUT input
tc(UP)
tw(UPH)
tw(UPL)
TAiOUT input (counter increment/
decrement select input)
TAiIN input (count on falling edge)
TAiIN input (count on rising edge)
th(TIN-UP) tsu(UP-TIN)
In event counter mode
TBiIN input
tc(TB)
tw(TBH)
tw(TBL)
ADTRG input
tc(AD)
tw(ADL)
CLKi
ISCLKi
tc(CK)
tw(CKH)
tw(CKL)
TXDi
ISTXDi
th(C-Q)
td(C-Q)
RXDi
ISRXDi
tsu(D-C)
th(C-D)
INTi input
tw(INL)
tw(INH)
NMI input
2 CPU clock cycles
+ 300 ns or more
2 CPU clock cycles
+ 300 ns or more
("L" width)
XIN input
tc
tw(L)tw(H)
tr tf
TAiIN input
TAiOUT input
In event counter mode with two-phase pulse input
tc(TA)
tsu(TAIN-TAOUT)tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAOUT-TAIN)