Datasheet

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 2. Central Processing Unit (CPU)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 23 of 85
2. Central Processing Unit (CPU)
R0H R0L
R1H R1L
R2
R3
R2
R3
A0
A1
SB
FB
Static base register
(1)
Frame base register
(1)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved
Processor interrupt priority level
Reserved
R0L
R1L
R2
R3
R2
R3
A0
A1
SB
FB
USP
INTB
ISP
PC
R0H
R1H
b31 b15
b23
b0
FLG
CDZSBOIU
IPL
b15
b0b8 b7
SVF
SVP
VCT
b23
b15 b0
DMD0
DMD1
DCT0
DCT1
DRC0
DRC1
DMA0
DMA1
DRA0
DRA1
DSA0
DSA1
b23
b15
b0b7
Address registers
(1)
User stack pointer
Interrupt stack pointer
Interrupt table register
Program counter
Flag register
General registers
High-speed interrupt registers
DMAC-associated registers
Flag save register
PC save register
Vector register
DMA mode registers
DMA transfer count registers
DMA transfer count reload registers
DMA memory address registers
DMA memory address reload registers
DMA SFR address registers
NOTE:
1. These registers comprise a register bank.
There are two sets of register banks (register bank 0 and register bank 1).
Data registers
(1)
Figure 2.1 shows the CPU registers.
The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There
are two sets of register banks.
Figure 2.1 CPU Register