Datasheet

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1. Overview
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 8 of 85
1.3 Block Diagram
Figure 1.2 shows a block diagram of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B).
Figure 1.2 M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Block Diagram
<VCC1>
<VCC1><VCC2>
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7
Internal peripheral functions
Three-phase motor
control circuit
Watchdog timer (15 bits)
8-bit D/A converters:
2 circuits
Intelligent I/O
Time measurement function:
8 channels
Waveform generation
function: 16 channels
(4)
Communication function:
clock synchronous serial
interface, UART, HDLC
data processing, IEBus
CAN modules:2 channels
(5)
Serial interface: 7 channels
(3)
X/Y converter:
16 bits X 16 bits
CRC calculation circuit
(CCITT):
X
16
+ X
12
+ X
5
+ 1
Clock generation circuits:
XIN-XOUT
XCIN-XCOUT
On-chip oscillator
PLL frequency synthesizer
DMAC: 4 channels
DMACII
10-bit A/D converter:
1 circuit
34 channels for input
(2)
Port P13
(1)
Port P12
(1)
Port P11
(1)
Port P15
(1)
Port P14
(1)
Port P10 Port P9 Port P8P8_5
Timers (16 bits)
Output (timer A): 5
Input (timer B): 6
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. 34 channels are available in the 144-pin package. 26 channels are available in the 100-pin package.
3. 6 channels are available in the 100-pin package.
4. 10 channels are available in the 100-pin package.
5. M32C/87A has 1 channel. M32C/87B has no CAN module.
8
8 8 8 8 8 8 8
8
ROM
Memory
Multiplier
M32C/80 Series CPU core
FLG
ISP
INTB
USP
PC
SVF
SVP
VCTSB
FB
R3
A1
A0
R2
R1H R1L
R1H R1L
R1H R1L
R0H R0L
<VCC2>
8
5 8 7 8 8 7
RAM