Datasheet

Page 71
78fo5002,10.luJ12.1.veR
)T58/C23M,58/C23M(puorG58/C23M
5. Electrical Characteristics (M32C/85)
BCLK
CSi
ADi
RD
-3ns.min
BHE
ADi
/DBi
30ns.min
td(BCLK-RD)
tsu(DB-BCLK)
tdz(RD-AD)
8ns.max
ALE
td(BCLK-ALE)
18ns.max
td(AD-ALE)
th(ALE-AD)
th(BCLK-RD)
th(RD-AD)
td(BCLK-AD)
th(BCLK-CS)
th(RD-CS)
th(BCLK-ALE)
tcyc
Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space and using the multiplexed bus)
0ns.min
BCLK
CSi
ADi
BHE
ADi
/DBi
WR,WRL,
WRH
ALE
th(BCLK-WR)
18ns.max
tac2(AD-DB)
[ Read Timing ] (2φ +2φ Bus Cycles)
Address
(1)
(1)
(1)
(1)
(1)
td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a)
t
h(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a)
t
h(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
t
ac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1)
t
ac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1)
NOTES:
1. Varies with operation frequency:
(1)
[ Write Timing ] (2φ +2φ Bus Cycles)
Address
Address
t
d(AD-ALE)=(tcyc/2 x n - 20)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n -10)ns.min
(if external bus cycle is aφ + bφ, n=a)
th(WR-AD)=(tcyc/2-10)ns.min,
t
h(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-20)ns.min
t
d(DB-WR)=(tcyc/2 x m-25)ns.min
(if external bus cycle is aφ + bφ, m=(b x 2)-1)
NOTES:
2. Varies with operation frequency:
Measurement Conditions:
• V
CC1=VCC2=3.0 to 3.6V
• Input high and low voltage:
V
IH=1.5V, VIL=0.5V
• Output high and low voltage:
V
OH=1.5V, VOL=1.5V
Vcc1=Vcc2=3.3V
18ns.max
td(BCLK-WR)
th(WR-AD)
(2)
th(BCLK-AD)
0ns.min
Data output
th(ALE-AD)
-2ns.min
td(BCLK-ALE)
th(BCLK-ALE)
18ns.max
18ns.max
0ns.min
th(WR-CS)
td(AD-ALE)
td(BCLK-CS)
td(BCLK-AD)
th(BCLK-CS)
td(DB-WR)
th(WR-DB)
tcyc
(2)
(2)
(2)
(2)
(2)
18ns.max
18ns.max
18ns.max
0ns.min
0ns.min
tac2(RD-DB)
-2ns.min
td(BCLK-CS)
th(RD-DB)
th(BCLK-AD)
0ns.min
Data input
Address
tcyc=
10
f
(BCLK)
9
Figure 5.8 VCC1=VCC2=3.3V Timing Diagram (2)