Datasheet

Page 68
78fo5002,10.luJ12.1.veR
5. Electrical Characteristics (M32C/85)
VCC1=VCC2=3.3V
)T58/C23M,58/C23M(puorG58/C23M
lobmySretemaraP
tnemerusaeM
noitidnoC
dradnatS
tinU
.niM.xaM
dt
)DA-KLCB( emiTyaleDtuptuOsserddA 81sn
ht
)DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0sn
ht
)DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA
)3(
0sn
ht
)DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA
)3(
)1etoN(sn
dt
)SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81sn
ht
)SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 0sn
ht
)SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC
)3(
0sn
ht
)SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC
)3(
)1etoN(sn
dt
)DR-KLCB( emiTyaleDtuptuOlangiSDR 81sn
ht
)DR-KLCB( emiTdloHtuptuOlangiSDR 3-sn
dt
)RW-KLCB( emiTyaleDtuptuOlangiSRW 81sn
ht
)RW-KLCB( emiTdloHtuptuOlangiSRW 0sn
dt
)RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(sn
ht
)BD-RW( )dradnatsRW(emiTdloHtuptuOataD
)3(
)1etoN(sn
wt
)RW( htdiWtuptuORW )2etoN(sn
t d(DB – WR) =
f
(BCLK)
10 x m
9
– 20
[ns] (if external bus cycle is aφ + bφ, m=b)
t
h(WR – DB) =
f
(BCLK) X 2
10
9
– 20
[ns]
t
h(WR – AD) =
f
(BCLK) X 2
10
9
– 10
[ns]
t
h(WR – CS) =
f
(BCLK) X 2
10
9
– 10
[ns]
t
w(WR) =
f
(BCLK) X 2
10 x n
9
– 15
[ns] (if external bus cycle is aφ + bφ, n=(b x 2)-1)
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles.
3. tc ns is added when recover
y
c
y
cle is inserted.
See Figure 5.2
Switching Characteristics
(VCC1=VCC2=3.0 to 3.6V, VSS = 0V at Topr = –20 to 85
o
C unless otherwise specified)
Table 5.40 Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space)