Datasheet

Page 59
78fo5002,10.luJ12.1.veR
5. Electrical Characteristics (M32C/85)
)T58/C23M,58/C23M(puorG58/C23M
Figure 5.3 VCC1=VCC2=5V Timing Diagram (1)
BCLK
RD
18ns.max
-5ns.min
Hi-Z
DB
0ns.min
0ns.min
tsu(DB-BCLK)
td(BCLK-RD)
26ns.min
(1)
CSi
td(BCLK-CS)
18ns.max
(1)
ADi
th(BCLK-AD)
-3ns.min
th(BCLK-CS)
-3ns.min
BHE
tcyc
td(BCLK-AD)
0ns.min
tac1(AD-DB)
(2)
WR,WRL,
WRH
18ns.max
-5ns.min
BCLK
CSi
td(BCLK-CS)
18ns.max
ADi
td(BCLK-AD)
18ns.max
-3ns.min
-3ns.min
tcyc
BHE
DBi
td(BCLK-WR)
th(WR-DB)
(3)
t d(DB-WR) =(tcyc x m-20)ns.min
(if external bus cycle is aφ+bφ, m=b)
t
h(WR-DB) =(tcyc/2-10)ns.min
t
h(WR-AD) =(tcyc/2-10)ns.min
t
h(WR-CS) =(tcyc/2-10)ns.min
t
w(WR) =(tcyc/2 x n-15)ns.min
(
if external bus c
y
cle is a
φ
+b
φ
,
n=
(
bx2
)
-1
)
Vcc 1 =Vcc 2 =5V
th(BCLK-RD)
th(RD-DB)
th(RD-AD)
th(RD-CS)
th(BCLK-WR)
th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)
(3)
th(WR-AD)
(3)
tw(WR)
(3)
tac1(RD-DB)
(2)
18ns.max
(1)
[ Read Timing ] (1φ +1φ Bus Cycle)
[ Write timing ] (1φ +1φ Bus Cycle)
NOTES:
3. Varies with operation frequency:
Measurement Conditions:
• V
CC1 =V CC2 =4.2 to 5.5V
• Input high and low voltage: V
IH =2.5V, V IL =0.8V
• Output high and low voltage: V
OH =2.0V, V OL =0.8V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for t
d(BCLK-AD) +t su(DB-BCLK) .
2. Varies with operation frequency:
t
ac1(RD-DB) =(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)+1)
t
ac1(AD-DB) =(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n=a+b)
td(DB-WR)
(3)
tcyc=
10
f
(BCLK)
9