Datasheet

Page 78
19fo6002,13.naJ14.1.veR
1410-3100B30JER
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Figure 5.15 VCC=3.3V Timing Diagram (6)
tcyc
18ns.max
td(BCLK-RAS)
18ns.max
td(BCLK-CAS)
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
0ns.min
tsu(CAS-RAS)
(1)
18ns.max
tcyc
td(BCLK-CAS)
tsu(CAS-RAS)
(1)
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
0ns.min
18ns.max
td(BCLK-RAS)
BCLK
DW
Vcc=3.3V
RAS
CASL
CASH
BCLK
DW
RAS
CASL
CASH
NOTES:
1. Varies with operation frequency.
t
su(CAS-RAS)=(tcyc/2-13)ns.min
Measurement Conditions:
• V
CC =3.0 to 3.6V
• Input high and low voltage: V
IH=1.5V, VIL=0.5V
• Output high and low voltage: V
OH=1.5V, VOL=1.5V
Refresh Timing (CAS-before-RAS refresh)
Memory Expansion Mode and Microprocessor Mode
NOTES:
1. Varies with operation frequency.
t
su(CAS-RAS)=(tcyc/2-13)ns.min
Refresh Timing (Self-refresh)