Datasheet

Page 77
19fo6002,13.naJ14.1.veR
1410-3100B30JER
)T38/C23M,38/C23M(puorG38/C23M
BCLK
DW
DB
MAi
Vcc=3.3V
RAS
CASL
CASH
Hi-Z
th(BCLK-DB)
-7ns.min
18ns.max
th(BCLK-CAD)
0ns.min
tcyc
td(BCLK-RAD)
th(BCLK-RAD)
0ns.min
18ns.max
td(BCLK-CAD)
18ns.max
td(BCLK-RAS)
18ns.max
td(BCLK-CAS)
tRP
(1)
18ns.max
td(BCLK-DW)
tsu(DB-CAS)
(1)
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
-3ns.min
th(BCLK-DW)
0ns.min
Row address
Column address
NOTES:
1. Varies with operation frequency.
t
h(RAS-RAD)=(tcyc/2-13)ns.min
t
RP=(tcyc/2 x 3-20)ns.min
t
su(DB-CAS)=(tcyc-20)ns.min
Measurement Conditions:
• V
CC=3.0 to 3.6V
• Input high and low voltage:
V
IH=1.5V, VIL=0.5V
• Output high and low voltage:
V
OH=1.5V, VOL=1.5V
Write Timing
Memory Expansion Mode and Microprocessor Mode
(With 2 wait states, when accessing the DRAM area)
th(RAS-RAD)
(1)
Figure 5.14 VCC=3.3V Timing Diagram (5)