Datasheet

Page 75
19fo6002,13.naJ14.1.veR
1410-3100B30JER
)T38/C23M,38/C23M(puorG38/C23M
BCLK
CSi
18ns.max
ADi
18ns.max
RD
18ns.max
-3ns.min
t h(BCLK-AD)
0ns.min
0ns.min
BHE
ADi
/DBi
0ns.min
18ns.max
0ns.min
BCLK
CSi
18ns.max
ADi
18ns.max
0ns.min
0ns.min
tcyc
BHE
ADi
/DBi
Data output
WR,WRL,
WRH
Address
Address
Data input
30ns.min
t d(BCLK-RD)
t h(WR-CS)
(1)
Address
t d(AD-ALE)
(1)
Address
t su(DB-BCLK)
t ac3(RD-DB)
(1)
t dz(RD-AD)
8ns.max
ALE
-2ns.min
t d(BCLK-ALE)
18ns.max
ALE
-2ns.min
t d(BCLK-ALE)
t h(ALE-AD)
(1)
Vcc=3.3V
t d(BCLK-CS)
t d(AD-ALE)
(1)
t h(ALE-AD)
(1)
t h(BCLK-RD)
t h(RD-AD)
(1)
t h(RD-DB)
t d(BCLK-AD)
t h(BCLK-CS)
t h(RD-CS)
(1)
t d(BCLK-WR)
t h(BCLK-WR)
t d(BCLK-CS)
t d(BCLK-AD)
t h(BCLK-AD)
t h(BCLK-CS)
t h(WR-AD)
()
t d(DB-WR)
(1)
t h(WR-DB)
(1)
t h(BCLK-ALE)
t h(BCLK-ALE)
tcyc
NOTES:
1. Varies with operation frequency.
t
d(AD-ALE) =(tcyc/2-20)ns.min
t
h(ALE-AD) =(tcyc/2-10)ns.min, t h(WR-AD) =(tcyc/2-10)ns.min
t
h(WR-CS) =(tcyc/2-10)ns.min, t h(WR-DB) =(tcyc/2-10)ns.min
t
d(DB-WR) =(tcyc/2 x m-25)ns.min
(m=3 with 2 wait states and m=5 with 3 wait states)
Measurement Conditions:
• V
CC =3.0 to 3.6V
• Input high and low voltage:
V
IH =1.5V, V IL =0.5V
• Output high and low voltage:
V
OH =1.5V, V OL =1.5V
NOTES:
1. Varies with operation frequency.
t
d(AD-ALE) =(tcyc/2-20)ns.min
t
h(ALE-AD) =(tcyc/2-10)ns.min, t h(RD-AD) =(tcyc/2-10)ns.min, t h(RD-CS) =(tcyc/2-10)ns.min
t
ac3(RD-DB) =(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states)
t
ac3(AD-DB) =(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Read Timing
Write Timing
Memory Expansion Mode and Microprocessor Mode
(with a wait state, when accessing an external memory and using the multiplexed bus)
18ns.max
t ac3(AD-DB)
(1)
Figure 5.12 VCC=3.3V Timing Diagram (3)