Datasheet

Page 74
19fo6002,13.naJ14.1.veR
1410-3100B30JER
)T38/C23M,38/C23M(puorG38/C23M
BCLK
ALE
18ns.max
-2ns.min
RD
18ns.max
-3ns.min
Hi-Z
DB
0ns.min
0ns.min
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
30ns.min
(1)
tac2(RD-DB)
(2)
CSi
td(BCLK-CS)
18ns.max
(1)
ADi
18ns.max
(1)
th(BCLK-AD)
0ns.min
th(BCLK-CS)
0ns.min
BHE
tcyc
td(BCLK-AD)
tac2(AD-DB)
(2)
WR,WRL,
WRH
18ns.max
0ns.min
BCLK
CSi
18ns.max
ADi
18ns.max
0ns.min
0ns.min
tcyc
BHE
DBi
td(BCLK-WR)
ALE
18ns.max
-2ns.min
Vcc=3.3V
th(BCLK-RD)
th(RD-DB)
th(RD-AD)
tsu(DB-BCLK)
th(RD-CS)
0ns.min
th(BCLK-WR)
td(BCLK-CS)
td(BCLK-AD)
td(BCLK-ALE)
th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)
(1)
td(DB-WR)
(1)
th(WR-DB)
(1)
th(WR-AD)
(1)
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait
states)
t
h(WR-DB)=(tcyc/2-10)ns.min
t
h(WR-AD)=(tcyc/2-10)ns.min
t
h(WR-CS)=(tcyc/2-10)ns.min
t
w(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait
states
)
NOTES:
1. Varies with operation frequency.
Measurement Conditions:
• V
CC=3.0 to 3.6V
• Input high and low voltage:
V
IH=1.5V, VIL=0.5V
• Output high and low voltage:
V
OH=1.5V, VOL=1.5V
NOTES:
1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed
for t
d(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency.
t
ac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states)
t
ac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states)
th(BCLK-ALE)
Read Timing
Write Timing
Memory Expansion Mode and Microprocessor Mode (with a wait state)
tw(WR)
(1)
Figure 5.11 VCC=3.3V Timing Diagram (2)