Datasheet

Page 73
19fo6002,13.naJ14.1.veR
1410-3100B30JER
)T38/C23M,38/C23M(puorG38/C23M
Figure 5.10 VCC=3.3V Timing Diagram (1)
BCLK
ALE
-2ns.min
RD
18ns.max
-3ns.min
Hi-Z
DB
0ns.min
0ns.min
td(BCLK-ALE)
th(BCLK-ALE)
tsu(DB-BCLK)
td(BCLK-RD)
30ns.min
(1)
CSi
td(BCLK-CS)
18ns.max
(1)
ADi
th(BCLK-AD)
0ns.min
th(BCLK-CS)
0ns.min
BHE
tcyc
td(BCLK-AD)
0ns.min
tac2(AD-DB)
(2)
WR,WRL,
WRH
18ns.max
0ns.min
BCLK
CSi
td(BCLK-CS)
18ns.max
ADi
td(BCLK-AD)
18ns.max
td(BCLK-ALE)
0ns.min
0ns.min
tcyc
BHE
td(DB-WR)
(1)
DBi
td(BCLK-WR)
ALE
-2ns.min
th(WR-DB)
(1)
t d(DB-WR) =(tcyc-20)ns.min
t
h(WR-DB) =(tcyc/2-10)ns.min
t
h(WR-AD) =(tcyc/2-10)ns.min
t
h(WR-CS) =(tcyc/2-10)ns.min
t
w(WR) =(tcyc/2-15)ns.min
Vcc=3.3V
th(BCLK-RD)
th(RD-DB)
th(RD-AD)
th(RD-CS)
th(BCLK-WR)
th(BCLK-ALE)
th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)
(1)
th(WR-AD)
(1)
tac2(RD-DB)
(2)
18ns.max
(1)
Read Timing
Write Timing
NOTES:
1. Varies with operation frequency.
Measurement Conditions:
• V
CC =3.0 to 3.6V
• Input high and low voltage: V
IH =1.5V, V IL =0.5V
• Output high and low voltage: V
OH =1.5V, V OL =1.5V
Memory Expansion Mode and Microprocessor Mode (with no wait state)
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for t
d(BCLK-AD) +t su(DB-BCLK) .
2. Varies with operation frequency:
t
ac2(RD-DB) =(tcyc/2-35)ns.max
t
ac2(AD-DB) =(tcyc-35)ns.max
18ns.max
tw(WR)
(1)
18ns.max