Datasheet

Page 63
19fo6002,13.naJ14.1.veR
1410-3100B30JER
)T38/C23M,38/C23M(puorG38/C23M
t h(BCLK–HOLD)
t su(HOLD–BCLK)
t d(BCLK–HLDA)
t d(BCLK–HLDA)
Hi–Z
Measurement Conditions:
• V
CC =4.2 to 5.5V
• Input high and low voltage: V
IH =4.0V, V IL =1.0V
• Output high and low voltage: V
OH =2.5V, V OL =2.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5
0 to P52
(Valid with a wait state or with no wait state)
(Valid only with a wait state)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Vcc=5V
Figure 5.9 VCC=5V Timing Diagram (8)