Datasheet

Page 60
19fo6002,13.naJ14.1.veR
1410-3100B30JER
)T38/C23M,38/C23M(puorG38/C23M
BCLK
DW
DB
MAi
t
h(RAS-RAD) =(tcyc/2-13)ns.min
t
RP =(tcyc/2 x 3-20)ns.min
t
su(DB-CAS) =(tcyc-20)ns.min
Vcc=5V
RAS
CASL
CASH
Hi-Z
th(BCLK-DB)
-7ns.min
18ns.max
th(BCLK-CAD)
-3ns.min
tcyc
td(BCLK-RAD)
th(BCLK-RAD)
-3ns.min
18ns.max
td(BCLK-CAD)
18ns.max
td(BCLK-RAS)
18ns.max
td(BCLK-CAS)
th(RAS-RAD)
(1)
tRP
(1)
18ns.max
td(BCLK-DW)
tsu(DB-CAS)
(1)
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
-3ns.min
th(BCLK-DW)
-5ns.min
Row address
Column address
NOTES:
1. Varies with operation frequency:
Measurement Conditions:
• V
CC =4.2 to 5.5V
• Input high and low voltage: V
IH =2.5V, V IL =0.8V
• Output high and low voltage: V
OH =2.0V, V OL =0.8V
Write Timing
Memory Expansion Mode and Microprocessor Mode
(When accessing the DRAM area)
Figure 5.6 VCC=5V Timing Diagram (5)