Datasheet

Page 59
19fo6002,13.naJ14.1.veR
1410-3100B30JER
)T38/C23M,38/C23M(puorG38/C23M
BCLK
DW
DB
MAi
Vcc=5V
RAS
CASL
CASH
Hi-Z
t ac4(CAS-DB)
(2)
18ns.max
t h(BCLK-CAD)
-3ns.min
tcyc
t d(BCLK-RAD)
t ac4(RAS-DB)
(2)
Row address
Column address
t h(BCLK-RAD)
-3ns.min
18ns.max
(1)
t d(BCLK-CAD)
18ns.max
(1)
t d(BCLK-RAS)
18ns.max
(1)
t d(BCLK-CAS)
t h(RAS-RAD)
(2)
t RP
(2)
t ac4(CAD-DB)
(2)
t h(BCLK-RAS)
-3ns.min
t h(BCLK-CAS)
-3ns.min
0ns.min
t su(DB-BCLK)
26ns.min
(1)
t h(CAS-DB)
Measurement Conditions:
• V
CC =4.2 to 5.5V
• Input high and low voltage: V
IH =2.5V, V IL =0.8V
• Output high and low voltage: V
OH =2.0V, V OL =0.8V
Read Timing
Memory Expansion Mode and Microprocessor Mode
(When accessing the DRAM area)
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for the following combinations.
t
d(BCLK-RAS) + t su(DB-BCLK)
t d(BCLK-CAS) + t su(DB-BCLK)
t d(BCLK-CAD) + t su(DB-BCLK)
2. Varies with operation frequency:
t
ac4(RAS-DB) =(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
t
ac4(CAS-DB) =(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
t
ac4(CAD-DB) =(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
t
h(RAS-RAD) =(tcyc/2-13)ns.min
t
RP =(tcyc/2 x 3-20)ns.min
Figure 5.5 VCC=5V Timing Diagram (4)