Datasheet

Page 18
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
A register bank comprises 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two
sets of register banks are provided.
Figure 2.1 CPU Register
b23
R0H R0L
R1H R1L
R2
R3
b31
R2
R3
A0
A1
SB
FB
USP
ISP
INTB
PC
High-Speed Interrupt Register
b15 b0
b23
SVF
SVP
VCT
DMAC Associated Register
b7 b0
b23
DMD0
DCT0
DCT1
b15
DRC0
DRC1
DMA0
DMA1
DMD1
DRA0
DRA1
Data Register
(1)
Address Register
(1)
Static Base Register
(1)
Frame Base Register
(1)
User Stack Pointer
Interrupt Stack Pointer
Interrupt Table Register
Program Counter
Flag Save Register
PC Save Register
Vector Register
DMA Mode Register
DMA Transfer Count Register
DMA Transfer Count Reload Register
DMA Memory Address Register
DMA SFR Address Register
DMA Memory Address Reload Register
NOTES:
1. A register bank comprises these registers. Two sets of register banks are provided.
General Register
b15 b0
b15 b0
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Space
Processor Interrupt Priority Level
Reserved space
FLG
Flag Register
IPL U I O B S Z D C
b7b8
DSA0
DSA1