Datasheet

Page 14
19fo6002,13.naJ14.1.veR
1410-3100B30JER
)T38/C23M,38/C23M(puorG38/C23M
Apply 3.0 to 5.5V to both VCC pin.
Apply 0V to the VSS pin.
(1)
Supplies power to the A/D converter. Connect the AVCC pin to VCC and the
AVSS pin to VSS
___________
The microcomputer is in a reset state when "L" is applied to the RESET pin
Switches processor mode. Connect the CNV SS pin to V SS to start up in single-
chip mode or to V CC to start up in microprocessor mode
Switches data bus width in external memory space 3. The data bus is 16
bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H".
Set to either. Connect the BYTE pin to VSS to use the microcomputer in
single-chip mode
Inputs and outputs data (D
0 to D7) while accessing an external memory
space with separate bus
Inputs and outputs data (D
8 to D15) while accessing an external memory
space with 16-bit separate bus
Outputs address bits A0 to A22
Outputs inversed address bit A23
Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0
to A7) by time-sharing while accessing an external memory space with
multiplexed bus
Inputs and outputs data (D
8 to D15) and outputs 8 middle-order address bits
(A
8 to A15) by time-sharing while accessing an external memory space with
16-bit multiplexed bus
_______ _______
Outputs CS0 to CS3 that are chip-select signals specifying an external space
________ _________ ______ ________ _____ ________
_________
Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and
WRH can be
______ _______
switched with WR and BHE by program
________ _________ _____
WRL, WRH and RD selected:
If external data bus is 16 bits wide, data is written to an even address in
________
external memory space when WRL is held "L".
_________
Data is written to an odd address when WRH is held "L".
_____
Data is read when RD is held "L".
______ ________ _____
WR, BHE and RD selected:
______
Data is written to external memory space when WR is held "L".
_____
Data in an external memory space is read when RD is held "L".
________
An odd address is accessed when BHE is held "L".
______ ________ _____
Select WR, BHE and RD for external 8-bit data bus.
ALE is a signal latching the address
__________
The microcomputer is placed in a hold state while the HOLD pin is held "L"
Outputs an "L" signal while the microcomputer is placed in a hold state
________
Bus is placed in a wait state while the RDY pin is held "L"
When DRAM area is accessed, outputs column and row addresses by time-sharing.
______ __________ __________
The DW signal becomes "L" when data is written to the DRAM area. CASL and CASH are
__________
signals indicating the timing to latch column addresses. The CASL signal becomes "L" when
__________
an even address is accessed. The CASH signal becomes "L" when an odd address is
________
accessed. RAS is a signal latching row addresses.
VCC
VSS
AVCC
AVSS
____________
RESET
CNV
SS
BYTE
D0 to D7
D8 to D15
A0 to A22
______
A23
A0/D0 to
A
7/D7
A8/D8 to
A
15/D15
______ ______
CS0 to CS3
________
______
WRL
/ WR
_________ ________
WRH / BHE
_____
RD
ALE
__________
HOLD
__________
HLDA
________
RDY
MA 0 to MA 12
______
DW
__________
CASL
__________
CASH
________
RAS
Power Supply
Analog Power
Supply
Reset Input
CNV
SS
Input to Switch
External Data Bus
Width
(2)
Bus Control
Pins
(2)
DRAM Bus
Control Pin
(2)
I
I
I
I
I
I/O
I/O
O
O
I/O
I/O
O
O
O
I
O
I
O
O
I : Input O : Output I/O : Input and output
NOTES:
1. Apply 4.2 to 5.5V to the VCC pin when using M32C/83T.
2. Bus control pins in M32C/83T cannot be used.
Classsfication Symbol I/O Type Function
1.6 Pin Description
Table 1.6 Pin Description (100-Pin and 144-Pin Packages)