Datasheet

M16C/6S Group Serial I/O
R01DS0201EJ0502 Rev.5.02 page 98 of 203
Dec 25, 2012
Figure 1.13.6. UCON Register and U0SMR to U2SMR Registers
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
UART transmit/receive control register 2
Symbol Address After reset
UCON 03B0
16 X00000002
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol
RW
Function
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
UART1 continuous
receive mode enable bit
UART1 CLK/CLKS
select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
U0IRS
U1IRS
U0RRM
U1RRM
UART1 CLK/CLKS
select bit 1 (Note)
Effective when CLKMD1 = “1”
0 : Clock output from CLK1
1 : Clock output from CLKS1
UART2 special mode register (i=0 to 2)
Symbol Address After reset
U0SMR to U2SMR 036F
16, 037316, 037716 X00000002
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol
Function
I
2
C mode select bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected (busy)
Arbitration lost detecting
flag control bit
0 : Other than I
2
C mode
1 : I
2
C mode
0 : Update per bit
1 :
Update per byte
IICM
ABC
BBS
Set to “0”
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
(Note1)
RCSP Separate UART0
CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS
0 supplied from the P64 pin)
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
RW
RW
RW
RW
RW
RW
RW
(b7)
RW
RW
RW
RW
RW
(b7)
0000
(b3-b6)
Reserved bit