Datasheet
M16C/6S Group Timer A
R01DS0201EJ0502 Rev.5.02 page 90 of 203
Dec 25, 2012
Figure 1.12.10. TAiMR Register in PWM Mode
Bit name
Timer Ai mode register (i= 0 to 4)
Symbol Address After reset
TA0MR to TA4MR 0396
16
to 039A
16
00
16
FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit
1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
or f
2
0 1 : f
8
1 0 : f
1 1 : Do not set
32
b7 b6
TCK1
TCK0
Count source select bit
RW
1 11
Must be set to “1” in PWM mode
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit
External trigger select
bit (Note 2)
0: Falling edge of input signal to TAi
IN
pin(Note 3)
1: Rising edge of input signal to TAi
IN
pin(Note 3)
RW
RW
RW
RW
RW
RW
RW
RW
(Note 1)
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
Note 1: TA0
OUT
pin is N-channel open drain output.
Note 2: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘00
2
’ (TAi
IN
pin input).
Note 3: The port direction bit for the TAi
There are not TA2
IN
and TA3
IN
.
IN
pin must be set to “0” (= input mode).