Datasheet

M16C/6S Group Timer A
R01DS0201EJ0502 Rev.5.02 page 79 of 203
Dec 25, 2012
Timer A
Figure 1.12.2 shows a block diagram of the timer A. Figures 1.12.3 to 1.12.5 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“0000
16.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Figure 1.12.3. TA0MR to TA4MR Registers
TAi Addresses TAj TAk
Timer A0 0387h - 0386h Timer A4 Timer A1
Timer A1 0389h - 0388h Timer A0 Timer A2
Timer A2 038Bh - 038Ah Timer A1 Timer A3
Timer A3 038Dh - 038Ch Timer A2 Timer A4
Timer A4 038Fh - 038Eh Timer A3 Timer A0
f1 or f2
f8
f3
2
TAiS
Increment / decrement
Select Count Source
• Timer(gate function):TMOD1 to TMOD0=00,
MR2=1
• Timer :TMOD1 to TMOD0=00, MR2=0
• One-Shot Timer :TMOD1 to TMOD0=10
• Pulse Width Modulation:TMOD1 to TMOD0=11
TAiIN
• Event counter:TMOD1 to TMOD0=01
Select clock
TAj Overflow
(1)
Pulse Output
Toggle Flip Flop
TAiOUT
Always decrement except
in event counter mode
8 low-order
bits
Reload Register
Counte
r
Low-Order Bits of Data Bus
TAiUD
Decrement
TAk Overflow
(1)
Polarity
Selector
00
01
10
TCK1 to TCK0
00
10
11
TAiTGH to TAiTGL
11
01
01
00
0
1
MR2
TMOD1 to TMOD
0
NOTES:
1. Overflow or underflow
TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR register
TAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4
TAiS : Bits in the TABSR register
TAiUD : Bits in the UDF register
TMOD1 to TMOD0,
MR2
i=0 to 4
j=i-1, except j=4 if i=0
k=i+1, except k=0 if i=4
8 high-
order
bit
s
To external
trigger circuit
High-Order Bits of Data Bus
Timer Ai mode register (i=0 to 4)
Symbol Address After reset
TA0MR to TA4MR 0396
16 to 039A16 0016
Bit name FunctionBit symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each
operation mode
Count source select bit
Operation mode select bit
RW
RW
RW
RW
RW
RW
RW
RW
Function varies with each
operation mod
e
Figure 1.12.2. Timer A Block Diagram