Datasheet

M16C/6S Group DMAC
R01DS0201EJ0502 Rev.5.02 page 75 of 203
Dec 25, 2012
Transfer unit Access address No. of read No. of write
cycles cycles
8-bit transfers Even 1 1
(DMBIT= “1”) Odd 1 1
16-bit transfers Even 1 1
(DMBIT= “0”) Odd 2 2
Table 1.11.2. DMA Transfer Cycles
Table 1.11.3. Coefficient j, k
Internal ROM, RAM SFR
No wait With wait
1
1
2
2
3
3
j
k
Notes:
1. Depends on the set value of CSE registe
r
2. Depends on the set value of PM20 bit in
P
2
2
1-wait
2
2-wait
2
2. DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the
number of DMA transfer cycles. Table 1.11.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k