Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 16-Bit 15 MHz I/O number 20

M16C/6S Group DMAC

R01DS0201EJ0502 Rev.5.02 page 74 of 203

Dec 25, 2012

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

(3) When the source read cycle under condition (1) has one wait state inserted

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(2) When the transfer unit is 16 bits and the source address of transfer is an odd address

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(4) When the source read cycle under condition (2) has one wait state inserted

Note: The same timing changes occur with the respective conditions at the destination as at the source.

Figure 1.11.5. Transfer Cycles for Source Read