Datasheet
M16C/6S Group DMAC
R01DS0201EJ0502 Rev.5.02 page 71 of 203
Dec 25, 2012
DMAi control register(i=0,1)
Symbol Address After reset
DM0CON 002C
16 00000X002
DM1CON 003C16 00000X002
Bit name FunctionBit symbol
Transfer unit bit select bit
b7 b6 b5 b4 b3 b2 b1 b0
0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMA request bit
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 2)
Destination address
direction select bit (Note 2)
0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
N
ote
2: A
t
l
east
o
n
e
o
f
t
h
e
DAD
a
n
d
D
S
D
b
i
ts
m
ust
be
“
0
”
(add
r
ess
d
ir
ect
i
o
n fix
ed)
.
(Note 1)
DMA1 request cause select register
Symbol Address After reset
DM1SL 03BA
16 0016
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bit
DSEL0
RW
DSEL1
DSEL2
DSEL3
Software DMA
request bit
DSR
DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)
0 0 0 02 Falling edge of INT1 pin –
0 0 0 12 Software trigger –
0 0 1 02 Timer A0 –
0 0 1 12 Timer A1 –
0 1 0 02 Timer A2 –
0 1 0 12 Timer A3 SI/O3
0 1 1 02 Timer A4 SI/O4
0 1 1 12 Two edges of INT1
1 0 0 02 –
1 0 0 12 –
1 0 1 02 UART0 transmit –
1 0 1 12 UART0 receive/ACK0 –
1 1 0 02 UART2 transmit –
1 1 0 12 UART2 receive/ACK2 –
1 1 1 02 –
–
–
–
–
1 1 1 12 UART1 receive/ACK1 –
Bit name
DMA request cause
expansion select bit
DMS
RW
RW
RW
RW
RW
RW
(b5-b4)
RW
RW
RW
RW
RW
RW
RW
(b7-b6)
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “0001
2”
(software trigger).
The value of this bit when read is “0” .
0: Basic cause of request
1: Extended cause of request
Refer to note
Figure 1.11.3. DM1SL Register, DM0CON Register, and DM1CON Registers