Datasheet

M16C/6S Group Watchdog Timer
R01DS0201EJ0502 Rev.5.02 page 67 of 203
Dec 25, 2012
Figure 1.10.2. WDC Register and WDTS Register
CPU
clock
Write to WDTS register
PM12 = 0
Watchdog timer
Set to
“7FFF
16 ”
1/128
1/16
CM07 = 0
WDC7 = 1
CM07 = 0
WDC7 = 0
CM07 = 1
HOLD
1/2
Prescaler
PM12 = 1
Watchdog timer
interrupt request
Rese
t
PM22 = 0
PM22 = 1
On-chip Oscillator clock
Internal RESET signal
(“L” active)
CM07: Bit in CM0 register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
PM22: Bit in PM2 register
Figure 1.10.1. Watchdog Timer Block Diagram
Setting the PM22 bit to “1” results in the following conditions
• The On-chip Oscillator starts oscillating, and the On-chip Oscillator clock becomes the watchdog timer
count source.
• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode.
Watchdog timer period =
Watchdog timer count (32768)
on-chip oscillator clock
Watchdog timer control register
Symbol Address After reset
WDC 000F
16 00XXXXXX 2
FunctionBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
High-order bit of watchdog timer
WDC7
Bit name
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Reserved bit
Must set to “0”
00
RO
RW
RW
(b4-b0)
(b6-b5)
Watchdog timer start register (Note)
Symbol Address After reset
WDTS 000E
16 Indeterminate
WO
b7 b0
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF 16 ”
regardless of whatever value is written.
RW
Note : Write to the WDTS register after the watchdog timer interrupt occurs.