Datasheet

M16C/6S Group Interrupts
R01DS0201EJ0502 Rev.5.02 page 61 of 203
Dec 25, 2012
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INT Interrupt
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INTi interrupt (i=0 to 3) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR register's IFSRi bit.
Figure 1.9.10 shows the IFSR and IFSR2A registers.
Figure 1.9.10. IFSR Register and IFSR2A Register
Interrupt request cause select register 2
Bit name Function
Bit symbol
RW
Symbol Address After reset
IFSR2A 035E
16 00XXXXXX 2
b7 b6 b5 b4 b3 b2 b1 b0
0 : reserved
1 : UART0 bus collision
detection
0 : reserved
1 : UART1 bus collision
detection
IFSR26
IFSR27
Interrupt request cause
select bit
Interrupt request cause
select bit
RW
RW
(b5-b0)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
Interrupt request cause select register
Bit name Function
Bit symbol
RW
Symbol Address After reset
IFSR 035F
16 00 16
IFSR0
b7 b6 b5 b4 b3 b2 b1 b0
INT0 interrupt polarity
switching bit
0 : SI/O3
1 : reserved
0 : SI/O4
1 : reserved
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
Interrupt request cause
select bit
Interrupt request cause
select bit
IFSR1
IFSR2
IFSR3
IFSR6
IFSR7
RW
RW
RW
RW
RW
RW
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 3)
(Note 2)
(Note 2)
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT3IC register’s POL bit
is set to “0” (= falling edge).
Note 2: Set this bit to “0” (= SI/O3, SI/O4)
Note 3: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
00
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
(b5-b4)