Datasheet

M16C/6S Group Interrupts
R01DS0201EJ0502 Rev.5.02 page 58 of 203
Dec 25, 2012
Figure 1.9.7. Operation of Saving Register
(2) SP contains odd number
[SP] (Odd)
[SP] – 1 (Even)
[SP] – 2(Odd)
[SP] – 3 (Even)
[SP] – 4(Odd)
[SP] – 5 (Even)
Address
Sequence in which order
registers are save
d
(2)
(1)
Finished saving registers
in four operations
.
(3)
(4)
(1) SP contains even number
[SP] (Even)
[SP] – 1(Odd)
[SP] – 2 (Even)
[SP] – 3(Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
PC
M
Stack
FLG
L
PC L
Sequence in which order
registers are save
d
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations
.
PC
M
Stack
FLG L
PC L
Saved, 8 bits at a time
FLG
H
PC H
FLG H
PC H
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
SP
(Note)
, at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
(Note)
is
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits
at a time. Figure 1.9.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.