Datasheet

M16C/6S Group Interrupts
R01DS0201EJ0502 Rev.5.02 page 57 of 203
Dec 25, 2012
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
1.9.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
Content of previous stack
Stack
[SP]
SPvalue before
interrupt occurs
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB L
SB
m
m – 1
m – 2
m – 3
m – 4
Address
FLG
L
Content of previous stack
Stack
FLG
H
PCH
[SP]
New SP value
Content of previous stack
m + 1
MSB L SB
PC
L
PC
M
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
Figure 1.9.6. Stack Status Before and After Acceptance of Interrupt Request