Datasheet

M16C/6S Group Interrupts
R01DS0201EJ0502 Rev.5.02 page 53 of 203
Dec 25, 2012
Figure 1.9.3. Interrupt Control Registers
Symbol Address After reset
INT3IC 0044
16 XX00X000 2
S4IC 0048 16 XX00X000 2
S3IC 0049 16 XX00X000 2
INT0IC to INT2IC 005D 16 to 005F 16 XX00X000 2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
ILVL0
IR
POL
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge (Notes 3, 4)
1 : Selects rising edge
Must always be set to “0”
ILVL1
ILVL2
Note 1: This bit can only be reset by writing "0" (Do not write "1").
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Note 3: If the IFSR register’s IFSRi bit (i = 0 to 5) is "1" (both edges), set the INTiIC register’s POL bit to "0 "(falling
edge).
Note 4: Set the S3IC or S4IC register’s POL bit to "0" (falling edge) when the IFSR register’s IFSR6 bit = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
(Note 1)
Interrupt control register (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Bit name FunctionBit symbol
RW
Symbol Address After reset
BCNIC 004A
16 XXXXX000 2
U0BCNIC (Note 3) 0047 16 XXXXX000 2
U1BCNIC (Note 3) 0046 16 XXXXX000 2
DM0IC, DM1IC 004B 16 , 004C 16 XXXXX000 2
S0TIC to S2TIC 0051 16 , 0053 16 , 004F 16 XXXXX000 2
S0RIC to S2RIC 0052 16 , 0054 16 , 0050 16 XXXXX000 2
TA0IC to TA4IC 0055 16 to 0059 16 XXXXX000 2
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
(Note 1)
Note 1: This bit can only be reset by writing "0" (Do not write "1").
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Note 3: Use the IFSR2A register to select.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
RW
RW
RW
RW
(b7-b4)
RW
RW
RW
RW
RW
RW
RW
RW
(b7-b6)