Datasheet

M16C/6S Group Clock Generation Circuit
R01DS0201EJ0502 Rev.5.02 page 43 of 203
Dec 25, 2012
Table 1.7.6. Allowed Transition and Setting
High-speed mode,
middle-speed mode
On-chip Oscillator mode
Stop mode
Wait mode
Current state
State after transition
See Table A
(10)
3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Setting Operation
CM06 = 0,
CPU clock no division mode
CM17 = 0 , CM16 = 0
CM06 = 0,
CPU clock division by 2 mode
CM17 = 0 , CM16 = 1
CM06 = 0,
CPU clock division by 4 mode
CM17 = 1 , CM16 = 0
CM06 = 1
CPU clock division by 8 mode
CM06 = 0,
CPU clock division by 16 mode
CM17 = 1 , CM16 = 1
CM21 = 0
Main clock
CM21 = 1 On-chip Oscillator clock selected
CM10 = 1 Transition to stop mode
wait Transition to wait mode
Hardware interrupt
Exit stop mode or wait mode
(6)
2
(7)
--
--
(8)
1
(9)
(8)
1
(9)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(3)
(3)
(3)
(3) (5)
(5)
(5)
(5)
(4)
(4)
(4)
(4)
State after transition
(10)
3
(10)(10)
Ta ble 1. State Transition with Main Clock Division Ration in High- or Middle-speed Mode
and On-chip Oscillator Mode.
Ta ble B. Setting and Operation
Notes:
1. Avoid making a transition when the CM21 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Set the CM06 bit to “1” (division by 8 mode) before transiting from On-chip Oscillator mode to high- or middle-speed mode.
3. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
--: Cannot transit
High-speed mode,
middle-speed mode
On-chip Oscillator
mode
Stop mode
Wait mode
See Table A
No
division
Divided
by 2
Divided
by 4
Divided
by 8
Divided
by 16
Current
state
No division
Divided by 4
Divided by 8
Divided by 16
Divided by 2