Datasheet

M16C/6S Group Clock Generation Circuit
R01DS0201EJ0502 Rev.5.02 page 42 of 203
Dec 25, 2012
Figure 1.7.8. State Transition in Normal Mode
CM07=0
CM17=0
CM06=0
CM16=0
CM07=0
CM17=0
CM06=0
CM16=1
CM07=0
CM17=1
CM06=0
CM16=0
CM07=0
CM06=1
CM07=0
CM17=1
CM06=0
CM16=1
High-speed mode
On-chip Oscillator mode
On-chip Oscillator
clock oscillation
CPU clock
CM21=0
(Note 4)
(Note 2)
(Note 3)
CM21=1
Main clock oscillation
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
Middle-speed mode
(divide by 2)
Middle-speed mode
(divide by 4)
Middle-speed mode
(divide by 8)
Middle-speed mode
(divide by 16)
CPU clock: f(XIN)
CPU clock: f(X IN )/2
CPU clock: f(X
IN )/4
CPU clock: f(X
IN )/8 CPU clock: f(X IN )/16
Notes:
1: Avoid making a transition when the CM20 bit in the CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2: Change CM17 and CM16 bits in the CM1 register before changing CM06 bit in the CM0 register
.
3: Transit in accordance with arrow.
4: Set the CM06 to “1” (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.