Datasheet
M16C/6S Group Clock Generation Circuit
R01DS0201EJ0502 Rev.5.02 page 41 of 203
Dec 25, 2012
Figure 1.7.7. State Transition to Stop Mode and Wait Mode
Reset
Medium-speed mode
(divided-by-8 mode)
High-speed, medium-
speed mode
Stop mode
Wait mode
Interrupt
CM10=1
Interrupt
Normal mode
CM10=1
Stop mode
All oscillators stopped
Interrupt
Wait mode
WAIT
instruction
(Note 1)
Interrupt
CPU operation stopped
Note 1: When the PM21 bit = 0 (system clock protective function unused).
Note 2: The On-chip Oscillator clock divided by 8 provides the CPU clock.
Note 3: Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21=0 (On-chip Oscillator turned off).
On-chip Oscillator mode
Wait mode
Interrupt
CM10=1
Interrupt
(Note 2)
Stop mode
WAIT
instruction
(Note 1)
WAIT
instruction
(Note 1)
Figure 1.7.7 shows the state transition from normal operation mode to stop mode and wait mode.