Datasheet

M16C/6S Group Overview
R01DS0201EJ0502 Rev.5.02 page 4 of 203
Dec 25, 2012
Block Diagram and PLC application Outline
Figure 1.1.1 is a block diagram of the M16C/6S group and PLC application Outline.
Figure 1.1.1. Block Diagram of Chip and PLC application Outline
10bit D/A
Buffer
Buffer
Compar
ator
BPF
SI1
100 to 200KHz
BPF
200 to 300KHz
BPF
300 to 400KHz
TXnRX
DCLK
DI
DO
CLR
nPHY_RES
P82/INT0
nINT
nCD1
nCD0
EXTCLK 15.36MHz
CLK_IN 46.08MHz
P40
P42
P95/CLK4
P96/SOUT4
P97/SIN4
P56
P54
P53
ROM
RAM
M16C Core IT800 Modem
Core
Inter
nal AFE
OPAMP
AMP1_IN
AMP1_OUT
CH1_INN
FB1
CH1_INP
Compar
ator
OPAMP
AMP2_IN
AMP2_OUT
CH2_INN
FB2
CH2_INP
Compar
ator
OPAMP
AMP3_IN
AMP3_OUT
CH3_INN
FB3
CH3_INP
VREF
PRE_BOUT
B
UFFER
OPAMP
VREF
PRE_INN
PRE_INP
Preamplifier
VccA
VssA
1bit-A/D x 3
IOUTC
IOUT
Rext
Line
coupling
SO
PLL module
Filter
s
Line
driv
er
XIN
XOUT
5.12MHz
R0H
R0L
R1H
R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
Multiplier
M16C/60 series 16-bit CPU core
Timer (16bits)
Output (TimerA) 5
UAR T or
Clock synchronous serial I/O
(8bits ✕ 3channels)
Clock synchronous serial I/O
(8bits ✕ 2channels)
Watchdog timer
(15bits)
DMAC
(2channels)
Port P1
P41
P11
P10
TS
TS
TEST_A
TEST_C
System clock generator
10
SI2
SI3
Port P
6
Port P7
Port P
8
Port P8
5
Port P
9
18
553
Flag register
Vector table
Program Counter
register
Stack Pointer
Block Diagram of Chip
Internal Peripherals
Memory
Inner
Po r
ts