Datasheet

M16C/6S Group Clock Generation Circuit
R01DS0201EJ0502 Rev.5.02 page 32 of 203
Dec 25, 2012
Figure 1.7.5. PCLKR Register and PM2 Register
FunctionBit symbol Bit name
Peripheral clock select register (Note)
Symbol Address When reset
PCLKR 025E
16
00000011
2
RW
b7 b6 b5 b4 b3 b2 b1 b0
PCLK0
Timers A, B clock select bit
(Clock source for the
timers A, B, and the dead
time timer)
0 : f
2
1 : f1
000
Reserved bit
Must set to
“0”
Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
000
PCLK1
SI/O clock select bit
(Clock source for UART0
to UART2, SI/O3, SI/O4)
0 : f
2SIO
1 : f1SIO
RW
RW
RW
(b7-b2)
Function
Bit symbol
Bit name
Processor mode register 2 (Note 1)
Symbol Address After reset
PM2 001E
16 XXX000002
RW
b7 b6 b5 b4 b3 b2 b1 b0
00
Reserved bit
Must set to “0”
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 3: Setting the PM21 bit to “1” results in the following conditions:
• The BCLK is not halted by executing the WAIT instruction.
• Writing to the following bits has no effect.
CM02 bit of CM0 register
CM05 bit of CM0 register (main clock is not halted)
CM07 bit of CM0 register
CM10 bit of CM1 register (stop mode is not entered)
CM11 bit of CM1 register
CM20 bit of CM2 register (oscillation stop, re-oscillation detection function settings do not change)
Note 4: Setting the PM22 bit to “1” results in the following conditions:
•
The On-chip Oscillator starts oscillating, and the On-chip Oscillator clock becomes the watchdog timer count source.
• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode or hold state.
RW
RW
PM21
(b7-b5)
System clock protective
bit
0 : Clock is protected by PRCR
register
1 : Clock modification disabled
PM22
WDT count source
protective bit
(Note 2, Note 3)
(Note 2, Note 4)
0 : CPU clock is used for the
watchdog timer count source
1 : On-chip Oscillator clock is used
for the watchdog timer count
source
RW
(b4-b3)
(b0)