Datasheet

M16C/6S Group Clock Generation Circuit
R01DS0201EJ0502 Rev.5.02 page 31 of 203
Dec 25, 2012
b7 b6 b5 b4 b3 b2 b1 b0
RW
CM20
CM21
Oscillation stop detection register (Note 1)
Symbol Address After reset
CM2
000C
16
0X000000 2 (Note 10)
Bit name
Function
Bit symbol
System clock select bit 2
(Notes 2, 3, 6, 10)
0: Oscillation stop, re-oscillation
detection function disabled
1: Oscillation stop, re-oscillation
detection function enabled
0: Main clock (On-chip Oscillator
turned off)
1: On-chip Oscillator clock
(On-chip Oscillator oscillating)
Oscillation stop, re-
oscillation detection bit
(Notes 7, 8, 9, 10)
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is set to “1” (On-chip Oscillator clock) if the main clock stop is detected.
Note 3: If the CM20 bit is “1” and the CM23 bit is “1” (main clock turned off), do not set the CM21 bit to “0”.
Note 4: This bit becomes “1” at main clock stop detection and main clock re-oscillation detection. When this bit
changes from “0” to “1”, there arise oscillation stop, re-oscillation detection interrupt. Use this register to
discriminate the causes for oscillation stop, re-oscillation detection interrupt and watchdog timer interrupt
in the interrupt processing program. By writing “0” in the program, this bit becomes “0”. (Even when “1” is
written in the program, no change is identified for the bit. Also, this bit is not set to “0” where there occur
oscillation stop, re-oscillation detection interrupt.) When the CM22 bit is “1”, no oscillation stop, re-
oscillation detection interrupt occur even if oscillation stop or re-oscillation is detected.
Note 5: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.
Note 6: Effective when the CM07 bit of CM0 register is “0”.
Note 7: When the PM21 bit of PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no
effect.
Note 8: Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to “1” (enable).
Note 9: Set the CM20 bit to “0” (disable) before setting the CM05 bit of CM0 register.
Note 10: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
CM22
CM23
Oscillation stop, re-
oscillation detection flag
0: Main clock stop, re-oscillation
not detected
1: Main clock stop, re-oscillation
detected
0: Main clock oscillating
1: Main clock turned off
X
IN monitor flag
(Note 4)
CM27
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
detection interrupt
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
Operation select bit
(when an oscillation stop,
re-oscillation is detected)
(Note 10)
RW
RW
RW
RW
RO
(b6)
(Note 5)
Reserved bit
(b5-b4)
Must set to “0”
RW
00
Figure 1.7.4. CM2 Register