Datasheet

M16C/6S Group Clock Generation Circuit
R01DS0201EJ0502 Rev.5.02 page 30 of 203
Dec 25, 2012
System clock control register 1 (Note 1)
Symbol Address After reset
CM1 0007
16
00100000
2
Bit
name
FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10
All clock stop control bit
(Notes 3, 4)
0 : Clock on
1 : All clocks off (stop mode)
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 3: When the CM20 bit of CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the
CM10 bit to “1”.
Note 4: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM10 bits has no effect.
When the PM22 bit of PM2 register is set to “1” (watchdog timer count source is On-chip Oscillator clock), writing to the CM10 bit
has no effect.
RW
CM16
CM17
Reserved bit
Must set to
“0”
Main clock division
select bit 1 (Note 2)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
0001 0
RW
RW
RW
RW
RW
(b4-b1)
Reserved bit
Must set to
“1”
(b5)
Figure 1.7.3. CM1 Register