Datasheet

M16C/6S Group Clock Generation Circuit
R01DS0201EJ0502 Rev.5.02 page 29 of 203
Dec 25, 2012
System clock control register 0 (Notes 1 and 4)
Symbol Address After reset
CM0 0006
16 010010002
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM02
CM06
WAIT peripheral function
clock stop bit (Note 3)
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode
Main clock division select
bit 0 (Notes 5, 13)
0 : CM16 and CM17 valid
1 : Division by 8 mode
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, On-chip Oscillator mode or On-chip Oscillator low power mode,
the CM06 bit is set to “1” (divide-by-8 mode).
Note 3: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM02 bits has no effect.
Note 4: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(2) Set the CM21 to “0”.
Note 5: During On-chip Oscillator low power dissipation mode, the divide-by-n value can be selected using the CM06 and CM17 to
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RW
RW
RW
RW
RW
(b1-b0)
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
(b4-b3)
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
(b7)
(b5)
Should be set to “0”.
Reserved bit
Should be set to “0”.
Reserved bit
00
Figure 1.7.2. CM0 Register