Datasheet

M16C/6S Group Clock Generation Circuit
R01DS0201EJ0502 Rev.5.02 page 28 of 203
Dec 25, 2012
Figure 1.7.1. Clock Generation Circuit
Pulse generation
circuit for clock
edge detection
and charge,
discharge control
Charge,
discharge
circuit
Reset
generating
circuit
Oscillation stop,
re-oscillation
detection interrupt
generating circuit
Main
clock
Oscillation stop
detection reset
CM27
0
1
CM21 switch signal
Oscillation stop,
re-oscillation
detection signal
Oscillation stop, re-oscillation detection circuit(Note)
Note. Even if X IN input stops, PLL does not stop. Oscillation stop, re-oscillation detect circuit does not function.
CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1: PCLK register bits
CM21, CM27 : CM2 register bits
CM02
CM10=1(stop mode)
Q
S
R
WAIT instruction
QS
R
Interrupt request level judgment output
RESET
Software reset
CPU clock
CM07 = 0
Divider
a
d
1/2 1/2 1/2 1/2
CM06=0
CM17–CM16=00
2
CM06=0
CM17–CM16=01
2
CM06=0
CM17–CM16=10
2
CM06=1
CM06=0
CM17–CM16=11
2
d
a
Details of divider
f 8
f 32
c
b
b
1/2
c
f32SIO
f8SIO
fAD
f1
e
e
1/2 1/4 1/8 1/16
1/32
PCLK0=1
CM21=1
CM21=0
On-chip
oscillator
On-chip
oscillator
clock
BCLK
PCLK0=0
f
2
f1SIO
PCLK1=1
PCLK1=0
f
2SIO
Main
clock
CM21
Oscillation
stop, re-
oscillation
detection
circuit
XOUTXIN
5.12MHz
Normal operation mode
(15.36MHz)
IT800 CLK_IN
1/3
Standard serial I/O mode
(5.12MHz)
PLL
46.08MHz