Datasheet

M16C/6S Group Processor Mode
R01DS0201EJ0502 Rev.5.02 page 25 of 203
Dec 25, 2012
Figure 1.6.3. PM1 Register
Figure 1.6.2. PM0 Register
Processor mode register 0 (Note 1)
Symbol Address After reset (Note 2)
PM0 0004
16
XXXX0X00
2 (CNV SS pin = “L”)
Bit name FunctionBit symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 0: Single-chip mode
0 1: Must not be set
1 0: Must not be set
1 1: Must not be set
b1 b0
PM03
PM01
(b2)
PM00
Processor mode bit
(Note 2)
Nothing is assigned. When write, set to
“0”.
When read, its content is indeterminate.
Software reset bit
Setting this bit to “1” resets the
microcomputer. When read, its content
is “0”.
RW
RW
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop
detection reset.
(b7-b4)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
Processor mode register 1 (Note 1)
Symbol Address After reset
PM1 0005
16 00XX10X0 2
Bit name FunctionBit symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
Note 2: PM12 bit is set to “1” by writing a “1” in a program. (Writing a “0” has no effect.)
Note 3: When PM17 bit is set to “1” (with wait state), one wait state is inserted when accessing the internal RAM,
internal ROM, or an external area.
PM17 Wait bit (Note 3)
0 : No wait state
1 : With wait state (1 wait)
Internal reserved area
expansion bit
PM13
Should be set to “0”.
Should be set to “1”.
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 2)
Watchdog timer function
select bit
PM12
RW
RW
RW
(b6)
Reserved bit
RW
001
(b2)
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
(b5-b4)
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
Should be set to “0”.
(b0)
Reserved bit