Datasheet

M16C/6S Group Reset
R01DS0201EJ0502 Rev.5.02 page 22 of 203
Dec 25, 2012
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Table 1.5.1. Pin Status When RESET Pin Level is ā€œLā€
Status
CNVSS = VSS
Pin name
P15,
P6
0 to P67,
P7
0, P71, P73,
P7
4, P76,
P8
0, P81,
P8
3, P84, P85,
P9
0 to P92,
TS
Input port
Figure 1.5.3. CPU Register Status After Reset
b15
b0
Data register(R0)
Address register(A0)
Frame base register(FB)
Program counter(PC)
Interrupt table register(INTB)
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
Flag register(FLG)
0000
16
0000
16
0000
16
CDZSBOIU
IPL
0000
16
0000
16
0000
16
0000
16
0000
16
b19
b0
Content of addresses FFFFE
16
to FFFFC
16
b15
b0
b15
b0
b15
b0
b7 b8
00000
16
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A1)
0000
16
0000
16
0000
16