Datasheet

M16C/6S Group Flash Memory Version
R01DS0201EJ0502 Rev.5.02 page 172 of 203
Dec 25, 2012
(6) DMA Transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
(7) Writing Command and Data
Write the command code and data at even addresses.
(8) Wait Mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing
the WAIT instruction.
(9) Stop Mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program BSET 0, CM1 ; Stop mode
JMP.B L1
L1:
Program after returning from stop mode